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US5453583A
Expired / Lapsed
US
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Interior bond pad arrangements for alleviating thermal stresses
Assignee: LSI Corp
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Filing: 1993-05-05
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Granted: 1995-09-26
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Expires: 2013-05-05
Abstract
Abstract A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads. Other aspects involve disposing the bond pads into an elongated pattern to minimize thermal displacement primarily in one direction, and orienting a lead frame or the like to accommodate any thermal migration of the bond pads in a controlled direction.
Inventors
- 👤 Michael D. Rostoker
- 👤 Nicholas F. Pasch
- 👤 Joe Zelayeta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:49
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/20; H10W72/29; H10W72/50; H10W72/541; H10W72/5449; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
94 words
Method of laying out bond pads on a semiconductor die, comprising: providing a semiconductor die having a total area, a substantially planar surface, and edges of the planar surface; defining on the planar surface, within a single boundary, a small, closed sub-area of the die having an area enclosed by the boundary which is substantially smaller than the total area of the die; and providing bond pads in the sub-area so that the bond pads are sufficiently close together to minimize thermal displacement of any given bond pad relative to any other bond pad.
Claim 2
Dependent Claim
94 words
Method of laying out bond pads on a semiconductor die, comprising: providing a semiconductor die having a total area, a substantially planar surface, and edges of the planar surface; defining on the planar surface, within a single boundary, a small, closed sub-area of the die having an area enclosed by the boundary which is substantially smaller than the total area of the die; and providing bond pads in the sub-area so that the bond pads are sufficiently close together to minimize thermal displacement of any given bond pad relative to any other bond pad.
Claim 3
Dependent Claim
33 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the area of the sub-area is less than one half of the total area of the die.
Claim 4
Dependent Claim
33 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the area of the sub-area is less than one third of the total area of the die.
Claim 5
Dependent Claim
33 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the area of the sub-area is less than one fifth of the total area of the die.
Claim 6
Dependent Claim
33 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the area of the sub-area is less than one tenth of the total area of the die.
Claim 7
Dependent Claim
33 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the area of the sub-area is less than one fiftieth of the total area of the die.
Claim 8
Dependent Claim
33 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the area of the sub-area is less than one hundredth of the total area of the die.
Claim 9
Dependent Claim
32 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the sub-area includes an interior area of the die and a peripheral portion of the die.
Claim 10
Dependent Claim
69 words
A method of laying out bond pads on a semiconductor die according to claim 1, further comprising: defining a ring-like peripheral area of the die on the planar surface along the edges of the planar surface; and defining an interior area of the die on the planar surface, said interior area enclosed by the peripheral area; wherein: the sub-area is completely contained within the interior area of the die.
Claim 11
Dependent Claim
39 words
A method of laying out bond pads on a semiconductor die according to claim 1, wherein: the sub-area is an elongated area; the bond pads are disposed in two parallel rows along a longitudinal dimension of the elongated area.
Claim 12
Dependent Claim
62 words
Method, according to claim 1, further comprising: determining locations for bond pads based on the position of underlying circuitry of the die; defining desired locations for bond pads, the bond pads being provided at the desired locations, at least a portion of the desired locations differing from the determined locations; and providing conductive paths between the determined locations and the desired locations.
Claim 13
Dependent Claim
18 words
Method, according to claim 11, wherein: the conductive paths are provided by existing conductive layers on the die.
Claim 14
Dependent Claim
18 words
Method, according to claim 11, wherein: the conductive paths are provided by additional conductive layers on the die.
Claim 15
Dependent Claim
69 words
A semiconductor device assembly comprising: a semiconductor die having a total area, a substantially planar surface, and edges of the planar surface; a small, closed sub-area of the die on the planar surface having an area which is substantially smaller than the total area of the die; and bond pads disposed in the sub-area to minimize thermal displacement of any given bond pad relative to any other bond pad.
Claim 16
Dependent Claim
69 words
A semiconductor device assembly comprising: a semiconductor die having a total area, a substantially planar surface, and edges of the planar surface; a small, closed sub-area of the die on the planar surface having an area which is substantially smaller than the total area of the die; and bond pads disposed in the sub-area to minimize thermal displacement of any given bond pad relative to any other bond pad.
Claim 17
Dependent Claim
39 words
A semiconductor device assembly according to claim 14, further comprising: a plurality of conductive leads disposed in close proximity to the bond pads; and an electrical connection formed between each of the conductive leads and a corresponding bond pad.
Claim 18
Dependent Claim
18 words
A semiconductor device assembly according to claim 15, wherein: the electrical connection is provided by a bond wire.
Claim 19
Dependent Claim
18 words
A semiconductor device assembly according to claim 15, wherein: the electrical connection is provided by a solder-bump-type connection.
Claim 20
Dependent Claim
25 words
A semiconductor device assembly according to claim 14, wherein: the sub-area includes an interior area of the die and a peripheral portion of the die.
Claim 21
Dependent Claim
62 words
A semiconductor device assembly according to claim 14, further comprising: a ring-like peripheral area of the die defined on the planar surface along the edges of the planar surface; and an interior area of the die defined on the planar surface, said interior area enclosed by the peripheral area; wherein: the sub-area is completely contained within the interior area of the die.
Claim 22
Dependent Claim
32 words
A semiconductor device assembly according to claim 14, wherein: the sub-area is an elongated area; the bond pads are disposed in two parallel rows along a longitudinal dimension of the elongated area.
Claim 23
Dependent Claim
28 words
A semiconductor device assembly according to claim 14, wherein: the bond pads are disposed along a straight line, said straight line substantially laterally centered on the planar surface.
Claim 24
Dependent Claim
78 words
A semiconductor device assembly according to claim 14, wherein: locations are determined for the bond pads based on the position of underlying circuitry of the die; desired locations are defined for the bond pads, at least a portion of the desired locations differing from the determined locations; the bond pads are disposed at the desired locations; and further comprising: conductive paths disposed between the determined locations and the portion of the desired locations differing from the determined locations.
Claim 25
Dependent Claim
21 words
A semiconductor device assembly according to claim 22, wherein: the conductive paths are provided by existing conductive layers on the die.
Claim 26
Dependent Claim
21 words
A semiconductor device assembly according to claim 22, wherein: the conductive paths are provided by additional conductive layers on the die.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |