US5457408A
Expired / Lapsed
US
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Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA
Assignee: AT&T Inc
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Filing: 1994-11-23
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Granted: 1995-10-10
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Expires: 2014-11-23
Abstract
Abstract A field programmable gate array (FPGA) which verifies that an incoming bitstream is intended for it prior to writing configuration data to programmable memory cells is described. The bitstream has an identification frame which includes an identification code for the targeted FPGA. A verification circuit in a memory controller verifies whether the bitstream is intended for the FPGA based upon the identification code. If the bitstream is intended for the FPGA, the configuration data is processed and stored in the programmable memory cells. If the bitstream is not intended for the FPGA, the FPGA may enter a standby mode, and the configuration process may be halted until a user resets the FPGA. The verification circuit can help prevent damage that may occur to the FPGA when bitstreams intended for a different size memory cell array are received by the FPGA.
Inventors
- 👤 Wai-Bor Leung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:42
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; G; G06; G06F; G06F30/00; G06F30/30; G06F30/34
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
60 words
A field programmable gate array (FPGA) comprising: an array of programmable logic cells (PLCs) having at least one programmable function unit (PFU) and having associated routing resources; a plurality of programmable input/output cells (PICs); a plurality of programmable memory cells; configuration logic; and a verification unit that verifies whether a bitstream received by said FPGA is intended for said FPGA.
Claim 2
Dependent Claim
60 words
A field programmable gate array (FPGA) comprising: an array of programmable logic cells (PLCs) having at least one programmable function unit (PFU) and having associated routing resources; a plurality of programmable input/output cells (PICs); a plurality of programmable memory cells; configuration logic; and a verification unit that verifies whether a bitstream received by said FPGA is intended for said FPGA.
Claim 3
Dependent Claim
13 words
The FPGA of claim 1 wherein said verification unit comprises a verification circuit.
Claim 4
Dependent Claim
18 words
The FPGA of claim 2 wherein said verification circuit comprises a comparator circuit having a hardwired identification code.
Claim 5
Dependent Claim
22 words
The FPGA of claim 3 wherein said comparator circuit compares an identification code contained in said bitstream to said hardwired identification code.
Claim 6
Dependent Claim
26 words
The FPGA of claim 4 wherein said verification circuit provides a signal indicating whether the identification code contained in said bitstream matches said hardwired identification code.
Claim 7
Dependent Claim
27 words
The FPGA of claim 5 wherein the FPGA enters a standby mode if the identification code contained in said bitstream does not match said hardwired identification code.
Claim 8
Dependent Claim
31 words
The FPGA of claim 4 further comprising a flip-flop circuit that provides a latched signal indicating that the identification code contained in said bitstream does not match said hardwired identification code.
Claim 9
Dependent Claim
28 words
The FPGA of claim 2 wherein said verification circuit compares an identification code contained in said bitstream to an identification code that is stored in said verification circuit.
Claim 10
Dependent Claim
28 words
The FPGA of claim 1 wherein said verification unit compares an identification code contained in said bitstream to an identification code that is stored in said verification unit.
Claim 11
Dependent Claim
32 words
The FPGA of claim 4 wherein said FPGA further comprises means for generating a signal indicating that said identification code contained in said bitstream is ready for verification by said verification circuit.
Claim 12
Dependent Claim
32 words
The FPGA of claim 4 wherein said FPGA further comprises circuitry for generating a signal indicating that said identification code contained in said bitstream is ready for verification by said verification circuit.
Claim 13
Dependent Claim
17 words
The FPGA of claim 1 wherein said plurality of programmable memory cells comprises random access memory (RAM).
Claim 14
Dependent Claim
19 words
The FPGA of claim 1 wherein said plurality of programmable memory cells comprises erasable programmable read only memory (EPROM).
Claim 15
Dependent Claim
20 words
The FPGA of claim 1 wherein said plurality of programmable memory cells comprises electrically erasable programmable read only memory (EEPROM).
Claim 16
Independent Claim
49 words
A method of using a field programmable gate array (FPGA) comprising the steps of: generating a bitstream comprising an identification code; receiving said bitstream in said field programmable gate array (FPGA); and verifying whether said bitstream is intended for said field programmable array (FPGA) based upon said identification code.
Claim 17
Independent Claim
49 words
A method of using a field programmable gate array (FPGA) comprising the steps of: generating a bitstream comprising an identification code; receiving said bitstream in said field programmable gate array (FPGA); and verifying whether said bitstream is intended for said field programmable array (FPGA) based upon said identification code.
Claim 18
Dependent Claim
26 words
The method of claim 15 wherein the step of verifying comprises the step of comparing said identification code to an identification code stored in said FPGA.
Claim 19
Dependent Claim
27 words
The method of claim 15 wherein the step of verifying comprises the step of comparing said identification code to an identification code permanently stored in said FPGA.
Claim 20
Dependent Claim
25 words
The method of claim 16 further including the step of generating a signal indicating that the identification code in said bitstream is ready for verification.
Claim 21
Dependent Claim
31 words
The method of claim 16 further including the step of entering a standby mode if the identification code in said bitstream does not match the identification code stored in said FPGA.
Claim 22
Dependent Claim
40 words
The method of claim 16 wherein said bitstream further comprises configuration data and wherein said method further comprises the step of processing said configuration data if the identification code in said bitstream matches the identification code stored in said FPGA.
Claim 23
Dependent Claim
29 words
The method of claim 15 further including the step of processing configuration data in said FPGA, wherein the step of verifying take place prior to the step of processing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |