Method for producing planar field emission structure

Claim 2

Method for producing planar field emission devices comprising the steps of: (a) patterning a metal cathode layer on the surface of an electrically-insulative substrate; (b) applying a thin resistive layer over the patterned cathode layer; (c) applying an etchable polymeric separation layer over the resistive layer; (d) depositing a thin anode base layer of a conductive metal over the surface of the separation layer; (e) etching via holes through predetermined spaced areas of the anode base layer; (f) electroplating the thin anode base layer with a conductive metal top layer to form a composite metal anode layer of increased thickness and strength and to reduce the diameter of each etched via hole; (g) electroplating the composite anode layer with a metal which differs from the conductive metals of the composite anode layer, to form a lift-off layer which is selectively-removable from said composite anode layer, and to further reduce the diameter of each etched and plated via hole; (h) exposing the polymeric separation layer, through each reduced-diameter via hole, to etching means to form via passages which extend down to the surface of the resistive layer and which have a diameter larger than the reduced diameter of each via hole; (i) directing a vaporized conductive cathode metal against the upper surface of the lift-off layer and through the reduced diameter via holes therein to deposit on said lift off layer and in a central area of the surface of the resistive layer within each via passage, and continuing such direction to form a conical conductive metal cathode which extends from the surface of the resistive layer into the reduced diameter via hole, within each said via passage; (j) selectively removing the lift-off layer which supports the layer of cathode metal accumulated thereon, and (k) removing the unsupported layer of cathode metal.

Claim 3

Method according to claim 1 in which the thin resistive layer of step (b) comprises a layer of amorphous silicon deposited by sputtering.

Claim 4

Method according to claim 1 in which the thin layer has a thickness between about 1 and 2 microns.

Claim 5

Method according to claim 1 in which the separation layer of step (c) comprises a layer of a polyimide polymer.

Claim 6

Method according to claim 1 in which the separation layer has a thickness between about 3 and 6 microns.

Claim 7

Method according to claim 1 in which the via holes formed in step (e) have diameters of 2 or more microns and the electroplating step (f) reduces the diameter of each said via hole to 1 or less microns.

Claim 8

Method according to claim 1 in which the anode top layer formed in step (f) has a thickness between about 0.2 and 1 micron.

Claim 9

Method according to claim 1 in which the composite anode layer of step (f) is removed from the surface of the separation layer, and steps (d), (e) and (f) are repeated to form a new composite anode layer having larger or smaller via holes.

Claim 10

Method according to claim 1 in which the cathode metal of step (i) comprises molybdenum.

Claim 11

Method according to claim 1 in which the lift-off layer is selectively removed in step (j) by de-plating means.

Claim 12

Method according to claim 1 in which the lift-off layer of step (g) has a thickness between about 0.2 and 1 micron.

Claim 13

Method according to claim 11 in which the lift-off layer comprises 0.5 micron thick copper.

Claim 14

Method according to claim 1 in which the etching means of step (h) comprises a reactive ion etching means.

Claim 15

Method according to claim 13 in which each via passage has a diameter greater than about 2 microns.

Claim 16

Method according to claim 1 in which the thin anode base layer of step (d) has a thickness between about 0.2 and 1 micron.

Claim 17

Method according to claim 15 in which the anode base layer comprises 0.5 micron thick nickel.

Claim 18

Method according to claim 16 in which the anode top layer also comprises 0.5 micron thick nickel.

Claim 19

Method for producing planar field emission devices comprising the steps of: (a) patterning a metal cathode layer on the surface of an electrically-insulative substrate; (b) applying a thin amorphous silicon resistive layer over the patterned cathode layer; (c) applying an etchable polymeric separation layer over the resistive layer; (d) depositing a 0.2 to 1 micron thick anode base layer of nickel over the surface of the separation layer; (e) etching via holes through predetermined spaced areas of the anode base layer, each said via hole having a diameter of 2 or more microns; (f) electroplating the thin anode base layer with a 0.2 to 1 micron thick conductive metal top layer of nickel top layer to form a composite metal anode layer of increased thickness and strength and to reduce the diameter of each etched via hole; (g) electroplating the composite anode layer with a 0.2 to 1 micron thick layer of copper to form a lift-off layer which is selectively-removable from said composite anode layer, and to further reduce the diameter of each etched and plated via hole; (h) exposing the polymeric separation layer, through each reduced-diameter via hole, to etching means to form via passages which extend down to the surface of the resistive layer and which have a diameter of about 2 or more microns; (i) directing a vaporized conductive cathode metal against the upper surface of the lift-off layer and through the reduced diameter via holes therein to deposit on said lift off layer and in a central area of the surface of the resistive layer within each via passage, and continuing such direction to form a conical conductive metal cathode which extends from the surface of the resistive layer into the reduced diameter via hole, within each said via passage; (j) selectively removing the lift-off layer which supports the layer of cathode metal accumulated thereon, and (k) removing the unsupported layer of cathode metal.

Claim 20

Method for producing planar field emission devices comprising the steps of: (a) patterning a metal cathode layer on the surface of an electrically-insulative substrate; (b) applying a thin amorphous silicon resistive layer over the patterned cathode layer; (c) applying an etchable polymeric separation layer over the resistive layer; (d) depositing a 0.2 to 1 micron thick anode base layer of nickel over the surface of the separation layer; (e) etching via holes through predetermined spaced areas of the anode base layer, each said via hole having a diameter of 2 or more microns; (f) electroplating the thin anode base layer with a 0.2 to 1 micron thick conductive metal top layer of nickel top layer to form a composite metal anode layer of increased thickness and strength and to reduce the diameter of each etched via hole; (g) electroplating the composite anode layer with a 0.2 to 1 micron thick layer of copper to form a lift-off layer which is selectively-removable from said composite anode layer, and to further reduce the diameter of each etched and plated via hole; (h) exposing the polymeric separation layer, through each reduced-diameter via hole, to etching means to form via passages which extend down to the surface of the resistive layer and which have a diameter of about 2 or more microns; (i) directing a vaporized conductive cathode metal against the upper surface of the lift-off layer and through the reduced diameter via holes therein to deposit on said lift off layer and in a central area of the surface of the resistive layer within each via passage, and continuing such direction to form a conical conductive metal cathode which extends from the surface of the resistive layer into the reduced diameter via hole, within each said via passage; (j) selectively removing the lift-off layer which supports the layer of cathode metal accumulated thereon, and (k) removing the unsupported layer of cathode metal.