Enhanced port activity monitor for an integrated multiport repeater

Claim 3

The monitoring circuit of claim 1 in which the status signals comprise: a link/loopback, a polarity/SQE, a partition, and a bitrate status.

Claim 4

A circuit for monitoring a plurality of ports of an Integrated Multiport Repeater, such that when the IMR is in minimum mode, the IMR receives carrier sense, signals for status information, serial output, signals for repeater management information, and a strobe, signal to provide signals that cause the IMR to read the CRS and SO signals from one of the plurality of ports, the monitor circuit comprising: a plurality of serially coupled media attachment units, circuits, a first MAU circuit receiving an input data stream packet of information and a last MAU providing a data output stream packet of information; an attachment unit interface, circuit serially coupled to the last one of the plurality of MAU circuits, the AUI circuit, upon detecting a particular bit in the data stream output, providing the strobe signal to the IMR; and means for causing the IMR to sense status signals from the SO signals in order to read from one of the plurality of ports in response to the STR signal provided by the AUI.

Claim 5

A circuit for monitoring a plurality of ports of an Integrated Multiport Repeater, such that when the IMR is in minimum mode, the IMR receives carrier sense, signals for status information, serial output, signals for repeater management information, and a strobe, signal to provide signals that cause the IMR to read the CRS and SO signals from one of the plurality of ports, the monitor circuit comprising: a plurality of serially coupled media attachment units, circuits, a first MAU circuit receiving an input data stream packet of information and a last MAU providing a data output stream packet of information; an attachment unit interface, circuit serially coupled to the last one of the plurality of MAU circuits, the AUI circuit, upon detecting a particular bit in the data stream output, providing the strobe signal to the IMR; and means for causing the IMR to sense status signals from the SO signals in order to read from one of the plurality of ports in response to the STR signal provided by the AUI.

Claim 6

The monitor circuit of claim 3 in which the AUI circuit is coupled in a feedback circuit between the MAU circuits and the IMR in order to circulate a low bit indicating which port status of the plurality of ports is monitored.

Claim 7

The monitoring circuit of claim 4 in which each of the plurality of MAU circuits corresponds to a port of the plurality of ports of the IMR.

Claim 8

The monitoring circuit of claim 5 in which each of the MAU circuits includes a shift register for receiving the input data stream.

Claim 9

The monitoring circuit of claim 6 in which the AUI circuit includes a shift register for receiving the output data stream.

Claim 10

The monitoring circuit of claim 7 in which the shift registers of the MAU and AUI circuits are coupled as a shift register.

Claim 11

The monitoring circuit of claim 8 in which a low bit circulating in the circular shift register causes the STR signal to be output to the IMR.

Claim 12

The monitoring circuit of claim 3 in which the causing means comprises: means for sampling a plurality of input signals; and means coupled to the sampling means for selecting a status bit to output from one of the plurality of ports.

Claim 13

The monitoring circuit of claim 10 in which the sampling means comprises a control circuit that samples a serial input signal SI, and a serial clock signal, SCLK.

Claim 14

The monitoring circuit of claim 11 in which the causing means further comprises means responsive to the selecting means for clearing the status bit.