US5460988A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for high density flash EPROM cell
Assignee: United Microelectronics Corp
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Filing: 1994-04-25
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Granted: 1995-10-24
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Expires: 2014-04-25
Abstract
Abstract A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:41
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
259 words
A method of forming a floating surrounding-gate memory cell, for an electrically programmable read-only memory (EPROM) or flash-memory, comprising the steps of: forming a well in a silicon substrate by implantation of a first conductivity type dopant; forming silicon mesas from said well, by anisotropically etching portions of said device-well, wherein said mesas remain at the unetched portions of said device-well; forming source regions in said device-well in the regions between said silicon mesas, by implanting with a second and opposite conductivity type dopant to said first conductivity type dopant, and simultaneously forming drain regions in the top of said silicon mesas by said implanting with a second and opposite conductivity type dopant; forming a first oxide layer over horizontal and vertical surfaces of said silicon mesas and over said source regions; anisotropically etching said first oxide layer to remove said first oxide layer from all said horizontal surfaces; forming a second oxide layer over said silicon mesas, said first oxide layer and said source regions, whereby a gate oxide is formed along said vertical surfaces of said silicon mesas, and a tunnel oxide that is thinner than said gate oxide is formed over said source regions; forming a first conductive layer over said gate oxide, thereby creating said surrounding-gate for said floating memory cell; forming an interpoly dielectric layer over the vertical surfaces of said first conductive layer, and horizontally over said source regions; and forming a second conductive layer over said interpoly dielectric layer, which acts as a control gate and word line for said memory cell.
Claim 2
Independent Claim
259 words
A method of forming a floating surrounding-gate memory cell, for an electrically programmable read-only memory (EPROM) or flash-memory, comprising the steps of: forming a well in a silicon substrate by implantation of a first conductivity type dopant; forming silicon mesas from said well, by anisotropically etching portions of said device-well, wherein said mesas remain at the unetched portions of said device-well; forming source regions in said device-well in the regions between said silicon mesas, by implanting with a second and opposite conductivity type dopant to said first conductivity type dopant, and simultaneously forming drain regions in the top of said silicon mesas by said implanting with a second and opposite conductivity type dopant; forming a first oxide layer over horizontal and vertical surfaces of said silicon mesas and over said source regions; anisotropically etching said first oxide layer to remove said first oxide layer from all said horizontal surfaces; forming a second oxide layer over said silicon mesas, said first oxide layer and said source regions, whereby a gate oxide is formed along said vertical surfaces of said silicon mesas, and a tunnel oxide that is thinner than said gate oxide is formed over said source regions; forming a first conductive layer over said gate oxide, thereby creating said surrounding-gate for said floating memory cell; forming an interpoly dielectric layer over the vertical surfaces of said first conductive layer, and horizontally over said source regions; and forming a second conductive layer over said interpoly dielectric layer, which acts as a control gate and word line for said memory cell.
Claim 3
Dependent Claim
94 words
The method of claim 1 wherein said first oxide layer vertical surfaces of said silicon islands and over said is formed by thermal oxidation at a temperature of about 850° C. for between about 10 to 30 minutes and said second oxide layer is formed by thermal oxidation at a temperature of between about 800 and 900° C. for between about 10 to 30 minutes, resulting in a thickness of said gate oxide of between about 120 to 200 Angstroms, and a thickness of said tunnel oxide of between about 60 to 100 Angstroms.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein said silicon mesas are formed to a height of between about 0.3 to 2.0 micrometers.
Claim 5
Dependent Claim
16 words
The method of claim 1, wherein said first conductive layer is formed of doped polycrystalline silicon.
Claim 6
Dependent Claim
31 words
The method of claim 1, wherein said source and drain regions are doped with arsenic at a concentration of between about 1 E 15 to 8 E 15 atoms/cm 2 .
Claim 7
Dependent Claim
22 words
The method of claim 1, wherein said interpoly dielectric layer is formed to a thickness of between about 150 to 300 Angstroms.
Claim 8
Dependent Claim
86 words
The method of claim 1, wherein said forming a second oxide layer comprises the steps of: forming a first layer of silicon oxide, adjacent to said first conductive layer, to a thickness of between about 50 and 150 Angstroms; forming a layer of silicon nitride, over said first layer of silicon oxide, to a thickness of between about 60 to 200 Angstroms; and forming a second layer of silicon oxide, over said layer of silicon nitride, to a thickness of between about 30 to 100 Angstroms.
Claim 9
Dependent Claim
29 words
The method of claim 1, wherein said second conductive layer is formed of doped polycrystalline silicon, and is formed to a thickness of between about 2000 to 4000 Angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-10-23 | 1999-04-24 | 1999-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-23 | 2003-04-24 | 2003-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-23 | 2007-04-24 | 2007-10-24 | $7700.00 | Window Closed / Lapsed |