US5465236A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory system with a plurality of erase blocks
Assignee: Toshiba Corp
•
Filing: 1994-08-23
•
Granted: 1995-11-07
•
Expires: 2014-08-23
Abstract
Abstract A nonvolatile semiconductor memory system including a memory cell array (1) having a plurality of floating gate memory cell transistors (MC) arranged in a matrix of rows and columns with plurality of bit lines (BL) connected to the drains of the floating gate memory cell transistors arranged in a same column and a plurality of word lines (WL) connected to the control gates of the floating gate memory cell transistors in a same row, and a refresh circuit for periodically refreshing the stored data in the floating gate memory cell transistor.
Inventors
- 👤 Kiyomi Naruke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:03
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/08; G11C16/26; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
152 words
A nonvolatile semiconductor memory system comprising: a memory cell array having a plurality of memory cell transistors arranged in a matrix of rows and columns with a plurality of bit lines connected to the drains of said memory cell transistors arranged in a same column and a plurality of word lines connected to the control gates of said memory cell transistors arranged in a same row, wherein said memory cell transistors are divided into a plurality of erase blocks comprising a plurality of said memory cell transistors and a plurality of refresh blocks comprising a plurality of said memory cell transistors, wherein the memory cell transistors of a respective erase block are addressed for erasing stored data and the memory cell transistors of a respective refresh block are independently addressed for refreshing of stored data; and a plurality of registers for temporally storing data which is read from said memory cell transistors.
Claim 2
Dependent Claim
152 words
A nonvolatile semiconductor memory system comprising: a memory cell array having a plurality of memory cell transistors arranged in a matrix of rows and columns with a plurality of bit lines connected to the drains of said memory cell transistors arranged in a same column and a plurality of word lines connected to the control gates of said memory cell transistors arranged in a same row, wherein said memory cell transistors are divided into a plurality of erase blocks comprising a plurality of said memory cell transistors and a plurality of refresh blocks comprising a plurality of said memory cell transistors, wherein the memory cell transistors of a respective erase block are addressed for erasing stored data and the memory cell transistors of a respective refresh block are independently addressed for refreshing of stored data; and a plurality of registers for temporally storing data which is read from said memory cell transistors.
Claim 3
Dependent Claim
24 words
The nonvolatile semiconductor memory system according to claim 1, wherein said erase blocks each have a size larger than that of said refresh blocks.
Claim 4
Dependent Claim
22 words
The nonvolatile semiconductor memory system according to claim 2, wherein said erase blocks are each twice as large as said refresh blocks.
Claim 5
Dependent Claim
31 words
The nonvolatile semiconductor memory system according to claim 1, wherein one of said refresh blocks includes a larger number of memory cell transistors than the number of said plurality of registers.
Claim 6
Dependent Claim
40 words
The nonvolatile semiconductor memory system according to claim 4, wherein the number of said memory cell transistors contained in said one refresh block is N times larger than the number of said plurality of registers, wherein N is an integer.
Claim 7
Dependent Claim
33 words
The nonvolatile semiconductor memory system according to claim 1, wherein each of said refresh blocks consists of one row of said memory cell transistors having gate electrodes connected to a respective word line.
Claim 8
Dependent Claim
33 words
The nonvolatile semiconductor memory system according to claim 1, wherein each of said erase blocks consists of two rows of said memory cell transistors having gate electrodes connected to two respective word lines.
Claim 9
Dependent Claim
17 words
The nonvolatile semiconductor memory system according to claim 1, wherein a number of said registers is eight.
References Cited (Backward Citations)
US5239505A
Cited
US5375094A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-06 | 1999-05-08 | 1999-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-06 | 2003-05-08 | 2003-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-06 | 2007-05-08 | 2007-11-07 | $7700.00 | Window Closed / Lapsed |