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US5465377A
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Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
Assignee: International Business Machines Corp
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Filing: 1993-09-24
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Granted: 1995-11-07
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Expires: 2013-09-24
Abstract
Abstract A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
Inventors
- 👤 Bartholomew Blaner
- 👤 Stamatis Vassiliadis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/30145; G06F9/30149; G06F9/30152; G06F9/3017; G06F9/3802; G06F9/3808; G06F9/3812; G06F9/3836; G06F9/3842; G06F9/3853; G06F9/3885
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
234 words
An apparatus for processing a series of instruction groups containing a sequence of compiled instructions for parallel execution, comprising: buffer means for receiving a series of instruction groups, each group containing a sequence of compiled instructions; categorization means responsive to the sequence of compiled instructions of each instruction group for: determining whether at least two adjacent instructions of the sequence of compiled instructions belong to predetermined categories of instructions; and providing first signals conditioned to indicate to which predetermined categories the at least two adjacent instructions of the sequence of compiled instructions belong; interlock means responsive to the sequence of compiled instructions for providing second signals conditioned to indicate whether interlocks exist between the at least two adjacent instructions of the sequence of compiled instructions; compounding signal means connected to the categorization and interlock means and responsive to the first and second signals for providing a compounding signal to indicate whether the at least two adjacent instructions of the sequence of compiled instructions belong to instruction categories compatible for execution in parallel and are interlock-free prior to an instruction fetch and decode cycle for instruction execution of said each instruction group during which cycle timing and selection of instructions for execution is determined; and storage means connected to the compounding signal means for receiving a plurality of compounding signals for the sequence of instructions and for storing instructions which are grouped for concurrent execution.
Claim 2
Independent Claim
234 words
An apparatus for processing a series of instruction groups containing a sequence of compiled instructions for parallel execution, comprising: buffer means for receiving a series of instruction groups, each group containing a sequence of compiled instructions; categorization means responsive to the sequence of compiled instructions of each instruction group for: determining whether at least two adjacent instructions of the sequence of compiled instructions belong to predetermined categories of instructions; and providing first signals conditioned to indicate to which predetermined categories the at least two adjacent instructions of the sequence of compiled instructions belong; interlock means responsive to the sequence of compiled instructions for providing second signals conditioned to indicate whether interlocks exist between the at least two adjacent instructions of the sequence of compiled instructions; compounding signal means connected to the categorization and interlock means and responsive to the first and second signals for providing a compounding signal to indicate whether the at least two adjacent instructions of the sequence of compiled instructions belong to instruction categories compatible for execution in parallel and are interlock-free prior to an instruction fetch and decode cycle for instruction execution of said each instruction group during which cycle timing and selection of instructions for execution is determined; and storage means connected to the compounding signal means for receiving a plurality of compounding signals for the sequence of instructions and for storing instructions which are grouped for concurrent execution.
Claim 3
Dependent Claim
59 words
The apparatus of claim 1, wherein the compounding signal means includes rule means responsive to the first and second signals for: testing the conditions of the first and second signals according to a set of rules, the set of rules establishing which categories of instructions can be executed in parallel and establishing exceptions to those rules resulting from interlocks.
Claim 4
Dependent Claim
18 words
The apparatus of claim 1, wherein the sequence of compiled instructions includes a portion of a cache line.
Claim 5
Dependent Claim
14 words
The apparatus of claim 1, wherein the categorization means includes means for decoding instructions.
Claim 6
Dependent Claim
31 words
The apparatus of claim 2, wherein the compounding signal means includes a programmable device for being selectively programmed to test the first and second signals according to the set of rules.
Claim 7
Dependent Claim
24 words
The apparatus of claim 2 further including a high-speed instruction memory means for storing the sequence of compiled instructions and compounding signals for execution.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-06 | 1999-05-08 | 1999-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-06 | 2003-05-08 | 2003-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-06 | 2007-05-08 | 2007-11-07 | $7700.00 | Window Closed / Lapsed |