Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a first electrode receiving a first logic voltage; a second electrode receiving a second logic voltage; main memory means for storing data, said main memory means having a first ferroelectric capacitor coupled to a first MOS transistor and said first electrode; dummy memory means for transferring data to and from said main memory means, said dummy memory means having a second capacitor coupled to a second MOS transistor and said second electrode; and means for inverting the logic voltage of the first electrode after turning off the second MOS transistor.

Claim 3

The semiconductor memory device of claim 1, further including means for (1) inverting the first logic voltage and the second logic voltage after turning off the second MOS transistor, and (2) turning off the first MOS transistor after the first electrode and the second electrode are inverted.

Claim 4

The semiconductor memory device of claim 1, further including: a first bit line coupled to the first NOS transistor; a second bit line coupled to the second MOS transistor; and means, (1) before one of (a) a start of writing and (b) a start of reading and (2) after one of (a) an end of writing, and (b) an end of reading of the main memory means, for (1) setting the second bit line at a certain logic voltage and activating the second MOS transistor, and (2) then setting the logic voltage of the second electrode at a reverse logic voltage of the certain logic voltage.

Claim 5

A semiconductor memory device comprising: an initializing control signal line; an initializing potential signal line; a first electrode having a first logic voltage; a second electrode having a second logic voltage; main memory means for storing data, said main memory means having a first ferroelectric capacitor coupled to a first MOS transistor and said first electrode; dummy memory means for transferring data to and from said main memory means, said dummy memory means having a second capacitor coupled to a second MOS transistor and said second electrode; and a third MOS transistor coupled to the initializing control signal line, the initializing potential signal line, and the second ferroelectric capacitor.

Claim 6

A semiconductor memory device comprising: an initializing control signal line; an initializing potential signal line; a first electrode having a first logic voltage; a second electrode having a second logic voltage; main memory means for storing data, said main memory means having a first ferroelectric capacitor coupled to a first MOS transistor and said first electrode; dummy memory means for transferring data to and from said main memory means, said dummy memory means having a second capacitor coupled to a second MOS transistor and said second electrode; and a third MOS transistor coupled to the initializing control signal line, the initializing potential signal line, and the second ferroelectric capacitor.

Claim 7

The semiconductor memory device of claim 4, wherein the initializing potential signal line is connected to a grounding potential.

Claim 8

The semiconductor memory device of claim 4, further including a first bit line coupled to the first MOS transistor; a second bit line coupled to the second MOS transistor; and means for setting said second bit line and said first bit line at a grounding potential before a start of one of (a) writing and (b) reading of the main memory means.

Claim 9

The semiconductor memory device of claim 4, further including means for (1) turning on the third MOS transistor after the second MOS transistor is turned off, and (2) turning off the first MOS transistor after the first logic voltage and the second logic voltage are inverted.

Claim 10

A semiconductor memory device of claim 1, further including a first bit line coupled to the first MOS transistor, said first bit line having a bit line logic voltage; and means for setting the first logic voltage of the first electrode at an inverse logic voltage of the bit line logic voltage before reading of the main memory means.

Claim 11

The semiconductor memory device of claim 4, further including a first bit line coupled to the first MOS transistor, said first bit line having a bit line logic voltage; and means for setting the first logic voltage of the first electrode at an inverse logic voltage of the bit line logic voltage before reading of the main memory means.

Claim 12

The semiconductor memory device of claim 1, wherein the second MOS transistor has a source coupled to the second ferroelectric capacitor and wherein said semiconductor memory device further includes a first bit line coupled to the first MOS transistor; a second bit line coupled to the second MOS transistor, said second bit line having a bit line logic voltage; and means for setting a source logic voltage at the source of the second MOS transistor and the second logic voltage at a inverse logic voltage of the bit line logic voltage before reading of the main memory means.

Claim 13

The semiconductor memory device of claim 8, wherein one of (a) the first logic voltage and (b) the second logic voltage is always the same.

Claim 14

The semiconductor memory device of claim 9, wherein one of (a) the first logic voltage and (b) the second logic voltage is always the same.

Claim 15

The semiconductor memory device of claim 10, wherein one of (a) the first logic voltage and (b) the second logic voltage is always the same.

Claim 16

The semiconductor memory device of claim 4, wherein the second MOS transistor has a source coupled to the second ferroelectric capacitor and wherein said semiconductor memory device further includes a first bit line coupled to the first MOS transistor; a second bit line coupled to the second MOS transistor, said second bit line having a bit line logic voltage; and means for setting a source logic voltage at the source of the second MOS transistor and the second logic voltage at a inverse logic voltage of the bit line logic voltage before reading of the main memory means.

Claim 17

The semiconductor memory device of claim 1, wherein the second MOS transistor has a source coupled to the second ferroelectric capacitor and a source logic voltage at the source of the second MOS transistor; and wherein the semiconductor memory device further includes a first bit line coupled to the first MOS transistor; a second bit line coupled to the second MOS transistor, said second bit line having a bit line logic voltage; and means for setting the bit line logic voltage and the second logic voltage at an inverse logic voltage of the source logic voltage before reading of the main memory means.

Claim 18

The semiconductor memory device of claim 4, wherein the second MOS transistor has a source coupled to the second ferroelectric capacitor and a source logic voltage at the source of the second MOS transistor; and wherein the semiconductor memory device further includes a first bit line coupled to the first MOS transistor; a second bit line coupled to the second MOS transistor, said second bit line having a bit line logic voltage; and means for setting the bit line logic voltage and the second logic voltage at an inverse logic voltage of the source logic voltage before reading of the main memory means.

Claim 19

The semiconductor memory device of claim 1, further including means for inverting the first logic voltage of the first electrode and the second logic voltage of the second electrode after turning on the first MOS transistor and the second MOS transistor.

Claim 20

The semiconductor memory device of claim 4, further including means for inverting the first logic voltage of the first electrode and the second logic voltage of the second electrode after turning on the first MOS transistor and the second MOS transistor.

Claim 21

The semiconductor memory device of claim 1, further including a first bit line coupled to the first NOS transistor; a second bit line coupled to the second MOS transistor; and means for (a) pre-charging the first line and the second bit line after turning on the first MOS transistor and the second MOS transistor, (b) terminating the pre-charging before a start of one of (a) reading and (b) writing of the main memory means, and (c) then inverting the first logic voltage of the first electrode and the second logic voltage of the second electrode.

Claim 22

The semiconductor memory device of claim 4, further including a first bit line coupled to the first NOS transistor; a second bit line coupled to the second MOS transistor; and means for (a) pre-charging the first line and the second bit line after turning on the first MOS transistor and the second MOS transistor, (b) terminating the pre-charging before a start of one of (a) reading and (b) writing of the main memory means, and (c) then inverting the first logic voltage of the first electrode and the second logic voltage of the second electrode.

Claim 23

The semiconductor memory device of claim 4, further including means for turning on the first MOS transistor and the second MOS transistor after inverting the logic voltages of the first electrode and the second electrode.

Claim 24

The semiconductor memory device of claim 1, further including means for turning on the first MOS transistor and the second MOS transistor after inverting the logic voltages of the first electrode and the second electrode.

Claim 25

The semiconductor memory device of claim 1, wherein the first electrode is coupled to the second electrode.

Claim 26

A semiconductor memory device comprising: an electrode; main memory means for storing data, said main memory means having a first ferroelectric capacitor coupled to a first MOS transistor and said electrode; and dummy memory means for transferring data to and from said main memory means, said dummy memory means having a second capacitor coupled to a second MOS transistor and said electrode.

Claim 27

A semiconductor memory device comprising: an electrode; main memory means for storing data, said main memory means having a first ferroelectric capacitor coupled to a first MOS transistor and said electrode; and dummy memory means for transferring data to and from said main memory means, said dummy memory means having a second capacitor coupled to a second MOS transistor and said electrode.

Claim 28

A semiconductor memory device comprising: an amplifier, a first word line and a second word line, a first bit line and a second bit line connected to the amplifier, a first plate electrode and a second plate electrode, a first ferroelectric capacitor having a first electrode and a second electrode, the second electrode coupled to the first plate electrode, a first MOS transistor having a gate coupled to the first word line, a source coupled to the first electrode of the first ferroelectric capacitor, and a drain coupled to the first bit line, a second ferroelectric capacitor having a first electrode and a second electrode, the second electrode couple to the second plate electrode, and a second MOS transistor having a gate coupled to the second word line, a source coupled to the first electrode of the second ferroelectric capacitor, and a drain coupled to the second bit line wherein the electric field between the first electrode and the second electrode of the second ferroelectric capacitor is always in a first direction including zero.

Claim 29

A semiconductor memory device comprising: an amplifier, a first word line and a second word line, a first bit line and a second bit line connected to the amplifier, a first plate electrode and a second plate electrode, a first ferroelectric capacitor having a first electrode and a second electrode, the second electrode coupled to the first plate electrode, a first MOS transistor having a gate coupled to the first word line, a source coupled to the first electrode of the first ferroelectric capacitor, and a drain coupled to the first bit line, a second ferroelectric capacitor having a first electrode and a second electrode, the second electrode couple to the second plate electrode, and a second MOS transistor having a gate coupled to the second word line, a source coupled to the first electrode of the second ferroelectric capacitor, and a drain coupled to the second bit line wherein the electric field between the first electrode and the second electrode of the second ferroelectric capacitor is always in a first direction including zero.

Claim 30

The semiconductor memory device as recited in claim 1, wherein an electric field is formed between the first electrode and the second electrode of the second ferroelectric capacitor, said electric field is oriented in a first direction when the second MOS transistor is activated.

Claim 31

The semiconductor memory device as recited in claim 1, wherein an electric potential is formed between the first electrode and the second electrode of the second ferroelectric capacitor and wherein the second MOS transistor is activated after the electric potential between the first electrode and the second electrode of the second ferroelectric capacitor is changed to a different electric potential.

Claim 32

The semiconductor memory device as recited in claim 1, wherein the second plate electrode has an electric potential which is changed after the second MOS transistor is activated.

Claim 33

The semiconductor memory device recited in claim 1, wherein the second plate electrode has an electric potential and wherein the second MOS transistor is turned on after the electric potential of the second plate electrode is changed.

Claim 34

A semiconductor memory device comprising: an amplifier, a first word line and a second word line, a first plate electrode and a second plate electrode, a first bit line and a second bit line connected to the amplifier, a first ferroelectric capacitor having a first electrode and a second electrode, the second electrode coupled to the first plate electrode, a first MOS transistor having a gate coupled to the first word line, a source coupled to the first electrode of the first ferroelectric capacitor, and a drain coupled to the first bit line, a second ferroelectric capacitor having a first electrode and a second electrode, the second electrode coupled to the first plate electrode, and a second MOS transistor having a gate coupled to a second word line, a source coupled to the first electrode of the second ferroelectric capacitor, and a drain coupled to the second bit line, an electric field formed between the first bit line and the second electrode of the first ferroelectric capacitor so that the electric field is (a) oriented in a first direction when the first MOS transistor is activated and (b) oriented in a second direction before the first MOS transistor is deactivated, said first direction is the opposite of said second direction.

Claim 35

A semiconductor memory device comprising: an amplifier, a first word line and a second word line, a first plate electrode and a second plate electrode, a first bit line and a second bit line connected to the amplifier, a first ferroelectric capacitor having a first electrode and a second electrode, the second electrode coupled to the first plate electrode, a first MOS transistor having a gate coupled to the first word line, a source coupled to the first electrode of the first ferroelectric capacitor, and a drain coupled to the first bit line, a second ferroelectric capacitor having a first electrode and a second electrode, the second electrode coupled to the first plate electrode, and a second MOS transistor having a gate coupled to a second word line, a source coupled to the first electrode of the second ferroelectric capacitor, and a drain coupled to the second bit line, an electric field formed between the first bit line and the second electrode of the first ferroelectric capacitor so that the electric field is (a) oriented in a first direction when the first MOS transistor is activated and (b) oriented in a second direction before the first MOS transistor is deactivated, said first direction is the opposite of said second direction.

Claim 36

A semiconductor memory device comprising: an amplifier, a first word line and a second word line, a first plate electrode and a second plate electrode, a first bit line and a second bit line connected to the amplifier, a first ferroelectric capacitor having a first electrode and a second electrode, the second electrode of the first ferroelectric capacitor coupled to the first plate electrode, a first MOS transistor having a gate coupled to the first word line, a source coupled to the first electrode of the first ferroelectric capacitor, and a drain coupled to the first bit line, a second ferroelectric capacitor having a first electrode and a second electrode, and the second electrode of the second ferroelectric capacitor coupled to the second plate electrode, a second MOS transistor having a gate coupled to the second word line, a source coupled to the first electrode of the second ferroelectric capacitor, and a drain coupled to the second bit line, a first electric field formed between the first bit line and the second electrode of the first ferroelectric capacitor so that the electric field is oriented in a first direction when the first MOS transistor is activated and orientated in a second direction before the first MOS transistor and the second MOS transistors are deactivated, said first electric field and said second electric field are oriented in opposite directions, and a second electric field formed between the second bit line and the second electrode of the second ferroelectric capacitor so that the second electric field is orientated in a third direction when the second MOS transistor is activated and the second electric field is oriented in the third direction after the first MOS transistor and the second MOS transistors are deactivated.

Claim 37

A semiconductor memory device comprising: an amplifier, a first word line and a second word line, a first plate electrode and a second plate electrode, a first bit line and a second bit line connected to the amplifier, a first ferroelectric capacitor having a first electrode and a second electrode, the second electrode of the first ferroelectric capacitor coupled to the first plate electrode, a first MOS transistor having a gate coupled to the first word line, a source coupled to the first electrode of the first ferroelectric capacitor, and a drain coupled to the first bit line, a second ferroelectric capacitor having a first electrode and a second electrode, and the second electrode of the second ferroelectric capacitor coupled to the second plate electrode, a second MOS transistor having a gate coupled to the second word line, a source coupled to the first electrode of the second ferroelectric capacitor, and a drain coupled to the second bit line, a first electric field formed between the first bit line and the second electrode of the first ferroelectric capacitor so that the electric field is oriented in a first direction when the first MOS transistor is activated and orientated in a second direction before the first MOS transistor and the second MOS transistors are deactivated, said first electric field and said second electric field are oriented in opposite directions, and a second electric field formed between the second bit line and the second electrode of the second ferroelectric capacitor so that the second electric field is orientated in a third direction when the second MOS transistor is activated and the second electric field is oriented in the third direction after the first MOS transistor and the second MOS transistors are deactivated.