Content addressable memory having match line transistors connected in series and coupled to current sensing circuit

Claim 1

A contents addressable memory comprising a plurality of memory cells arranged in rows and columns, respective first and second bit lines associated with each column of said plurality of memory cells, means for applying address bit values to said respective bit lines, each memory cell comprising: electric circuit means for storing a binary value as a potential difference between first and second nodes of said electric circuit means; first, second and third transistors each having an input/output path and a control electrode for controlling current flow in said input/output path; means connecting the control electrodes of said first and second transistors to said first and second nodes respectively; and means connecting the control electrode of said third transistor to said first and second bit lines by way of the input/output paths of said first and second transistors respectively, means connecting the input/output paths of the respective third transistors of the memory cells of a row in series to form a matchline path for said row, and current sensing means responsive to current flow in a said matchline path associated with any of said rows of memory cells to detect a match between the address bit values applied to said bit lines and the binary values stored in the respective electric circuit means of the memory cells of said row.