Low dielectric constant insulation layer for integrated circuit structure and method of making same

Claim 2

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises: a) forming on an integrated circuit structure, an insulation layer consisting essentially of: i) a non-extractable insulation material selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, and mixtures of same; and ii) an extractable material selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide; and b) thereafter forming a porous structure in said insulation layer by removing said extractable material from said insulation layer, thereby reducing the dielectric constant of said insulation layer; to thereby form said low dielectric constant insulation layer.

Claim 3

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises: a) forming a composite layer comprising one or more non-extractable insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide; and b) extracting said one or more extractable materials leaving a porous structure comprising said one or more non-extractable insulation materials thereby forming said low dielectric constant insulation layer.

Claim 4

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises: a) forming a composite layer comprising one or more non-extractable insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide; and b) extracting said one or more extractable materials leaving a porous structure comprising said one or more non-extractable insulation materials thereby forming said low dielectric constant insulation layer.

Claim 5

The process of claim 2 wherein said non-extractable insulation material comprises at least 5 wt. % of said composite layer prior to said removal step.

Claim 6

The process of claim 2 wherein said step of forming said composite layer further comprises forming said composite layer with one or more optional dopants present.

Claim 7

The process of claim 2 including the further step of heating said composite layer to planarize said layer prior to said extraction step.

Claim 8

The process of claim 2 including the further steps of: a) forming one or more lower non-porous insulation layers on said integrated circuit structure prior to said step of forming said composite layer, to thereby prevent downward migration of impurities from said porous structure into said integrated circuit structure; and b) forming one or more upper solid insulation layers over said low dielectric constant insulation layer after said extraction step to thereby prevent migration of impurities from said porous structure into said integrated circuit structure.

Claim 9

The process of claim 2 wherein said step of forming said composite layer on said semiconductor wafer further comprises depositing said composite layer on said wafer by a chemical vapor deposition process.

Claim 10

The process of claim 7 wherein said step of forming said composite layer on said semiconductor wafer by a chemical vapor deposition process further comprises depositing said composite layer while maintaining a plasma in said vacuum chamber.

Claim 11

The process of claim 2 wherein said step of forming said composite layer further comprises depositing on said semiconductor wafer a mixture comprising: a) an oxide of silicon, comprising said insulation material; b) an oxide of germanium, comprising said extractable material; and c) optionally one or more dopants.

Claim 12

The process of claim 2 wherein said extraction step comprises contacting said composite layer with a first liquid which is a solvent for said one or more extractable materials and not a solvent for said one or more non-extractable insulation materials.

Claim 13

The process of claim 10 wherein said composite layer is contacted with said first liquid for a period of at least about 1 minute to remove said one or more extractable materials therefrom.

Claim 14

The process of claim 11 wherein said extraction step further comprises removing said first liquid and said one or more extractable materials dissolved therein from said composite layer by rinsing said composite layer in a second liquid which is miscible with said first liquid and also is not a solvent for said one or more non-extractable insulation materials.

Claim 15

The process of claim 12 wherein said second liquid is removed from said composite layer in a vacuum chamber.

Claim 16

The process of claim 13 wherein said vacuum chamber, in which said second liquid is removed from said composite layer, is maintained at a pressure within a range of from about 0.1 Torr to about 100 Torr.

Claim 17

The process of claim 14 wherein said wafer is maintained at a wafer temperature within a range of from about ambient temperature to just below the vaporization temperature of said second liquid, while said wafer is in said vacuum chamber in which said second liquid is removed from said composite layer.

Claim 18

The process of claim 15 wherein said wafer is maintained for a period of at least about 10 minutes in said vacuum chamber in which said second liquid is removed from said composite layer.

Claim 19

The process of claim 6 including the further steps of: a) forming one or more contact openings in said one or more lower solid insulation layers, said low dielectric constant insulation layer, and said one or more upper solid insulation layers; b) filling said contact openings with conductive material; and c) forming a patterned metal layer over an upper surface of said one or more upper solid insulation layers.

Claim 20

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises: a) forming one or more lower solid insulation layers on said integrated circuit structure; b) forming over said one or more lower solid insulation layers a composite layer comprising one or more insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide; c) removing said one or more extractable materials leaving a porous structure comprising said low dielectric constant insulation layer; and d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer; whereby said lower and upper solid insulation layers respectively prevent migration of impurities from said porous structure into said integrated circuit structure.

Claim 21

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises: a) forming one or more lower solid insulation layers on said integrated circuit structure; b) forming over said one or more lower solid insulation layers a composite layer comprising one or more insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide; c) removing said one or more extractable materials leaving a porous structure comprising said low dielectric constant insulation layer; and d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer; whereby said lower and upper solid insulation layers respectively prevent migration of impurities from said porous structure into said integrated circuit structure.

Claim 22

A process for forming a low dielectric constant insulation layer as a portion of an integrated circuit structure on a semiconductor wafer which comprises: a) forming on said semiconductor wafer an insulation layer consisting essentially of a mixture of silicon oxide, germanium oxide, and optionally one or more dopants; and b) thereafter further processing said insulation layer to form a porous structure therein by removing said germanium oxide from said insulation layer to reduce the dielectric constant of said insulation layer; to thereby form said low dielectric constant insulation layer.

Claim 23

A process for forming a low dielectric constant insulation layer as a portion of an integrated circuit structure on a semiconductor wafer which comprises: a) forming on said semiconductor wafer an insulation layer consisting essentially of a mixture of silicon oxide, germanium oxide, and optionally one or more dopants; and b) thereafter further processing said insulation layer to form a porous structure therein by removing said germanium oxide from said insulation layer to reduce the dielectric constant of said insulation layer; to thereby form said low dielectric constant insulation layer.

Claim 24

A process for forming a low dielectric constant insulation layer as a portion of an integrated circuit structure on a semiconductor wafer which comprises: a) forming one or more lower solid insulation layers on said semiconductor wafer; b) forming a composite layer comprising a silicon oxide non-extractable insulation material and a germanium oxide extractable material; c) removing said germanium oxide extractable material leaving a porous structure comprising said silicon oxide non-extractable insulation material to form said low dielectric constant insulation layer; and d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer after said extraction step; whereby said lower and upper solid insulation layers respectively inhibit downward or upward migration of impurities from said porous structure into other portions of said integrated circuit structure.

Claim 25

A process for forming a low dielectric constant insulation layer as a portion of an integrated circuit structure on a semiconductor wafer which comprises: a) forming one or more lower solid insulation layers on said semiconductor wafer; b) forming a composite layer comprising a silicon oxide non-extractable insulation material and a germanium oxide extractable material; c) removing said germanium oxide extractable material leaving a porous structure comprising said silicon oxide non-extractable insulation material to form said low dielectric constant insulation layer; and d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer after said extraction step; whereby said lower and upper solid insulation layers respectively inhibit downward or upward migration of impurities from said porous structure into other portions of said integrated circuit structure.

Claim 26

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises: a) forming one or more lower solid insulation layers on said integrated circuit structure; b) forming a composite layer comprising one or more non-extractable insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide; c) removing said one or more extractable materials leaving a porous structure comprising said one or more non-extractable insulation materials to form said low dielectric constant insulation layer; and d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer after said extraction step; e) forming one or more contact openings in said one or more lower solid insulation layers, said low dielectric constant insulation layer, and said one or more upper solid insulation layers; f) filling said contact openings with conductive material; and g) forming a patterned metal layer over an upper surface of said one or more upper solid insulation layers.

Claim 27

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises: a) forming one or more lower solid insulation layers on said integrated circuit structure; b) forming a composite layer comprising one or more non-extractable insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide; c) removing said one or more extractable materials leaving a porous structure comprising said one or more non-extractable insulation materials to form said low dielectric constant insulation layer; and d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer after said extraction step; e) forming one or more contact openings in said one or more lower solid insulation layers, said low dielectric constant insulation layer, and said one or more upper solid insulation layers; f) filling said contact openings with conductive material; and g) forming a patterned metal layer over an upper surface of said one or more upper solid insulation layers.