Voltage reference circuit with a common gate output stage

Claim 2

An integrated circuit for generating an output voltage, the circuit comprising: a. a current mirror comprising a reference node and a mirrored node, wherein during operation current through the reference node is equal to current through the mirrored node; b. biasing means for establishing a current through the reference node; c. a first regulator for regulating current through the mirrored node, the first regulator comprising a first control terminal coupled to the reference node; and d. an output stage for regulating an output current so that the output voltage is generated across a load resistor when the output current passes therethrough, the output stage comprising: (1) a second regulator for regulating the output current, the second regulator comprising a second control terminal coupled to the reference node; and (2) a third regulator in series with the second regulator for regulating the output current, the third regulator comprising a third control terminal coupled to the mirrored node.

Claim 3

The integrated circuit of claim 1 wherein the current mirror further comprises a switch for interrupting current flow through the reference node.

Claim 4

The integrated circuit of claim 2 further comprising a bootstrap circuit coupled to the switch to operate the switch so that during operation, current through the mirrored node is nonzero.

Claim 5

The integrated circuit of claim 1 wherein the current mirror comprises a pair of mirror circuits coupled in series.

Claim 6

The integrated circuit of claim 4 wherein the current mirror comprises four field effect transistors intercoupled to form the pair of mirror circuits coupled in series.

Claim 7

The integrated circuit of claim 1 wherein the biasing means comprises a power supply in series with a resistor.

Claim 8

The integrated circuit of claim 1 wherein the first regulator comprises a field effect transistor having a first gate, and the first control terminal is coupled to the first gate.

Claim 9

The integrated circuit of claim 1 wherein the second regulator comprises a field effect transistor having a second gate, and the second control terminal is coupled to the second gate.

Claim 10

The integrated circuit of claim 1 wherein the third regulator comprises a field effect transistor having a third gate, and the third control terminal is coupled to the third gate.

Claim 11

An integrated circuit operative between a first potential and a second potential, the circuit for generating an output voltage, the circuit comprising: a. a first device having a first resistance, the first device coupled between the first potential and a first network node; b. a first field effect transistor comprising: (1) a first gate coupled to the first node; and (2) a first channel; c. a second field effect transistor comprising: (1) a second gate; and (2) a second channel, the first channel and the second channel being sequentially coupled in series between the first potential and the second potential; d. a second network node in series between the first channel and the second channel; e. a third field effect transistor comprising: (1) a third gate coupled to a third network node, the third node coupled to the first node; (2) a third channel coupled between the third node and the second potential; f. a second device having a second resistance, the second device coupled in series between a fourth network node and the second potential; g. a fourth field effect transistor comprising: (1) a fourth gate coupled to the first gate; and (2) a fourth channel; and h. a fifth field effect transistor comprising: (1) a fifth gate coupled to the second node; and (2) a fifth channel, the fourth channel and the fifth channel being sequentially coupled in series between the first potential and the fourth node so that in operation the output voltage is provided at the fourth node.

Claim 12

An integrated circuit operative between a first potential and a second potential, the circuit for generating an output voltage, the circuit comprising: a. a first device having a first resistance, the first device coupled between the first potential and a first network node; b. a first field effect transistor comprising: (1) a first gate coupled to the first node; and (2) a first channel; c. a second field effect transistor comprising: (1) a second gate; and (2) a second channel, the first channel and the second channel being sequentially coupled in series between the first potential and the second potential; d. a second network node in series between the first channel and the second channel; e. a third field effect transistor comprising: (1) a third gate coupled to a third network node, the third node coupled to the first node; (2) a third channel coupled between the third node and the second potential; f. a second device having a second resistance, the second device coupled in series between a fourth network node and the second potential; g. a fourth field effect transistor comprising: (1) a fourth gate coupled to the first gate; and (2) a fourth channel; and h. a fifth field effect transistor comprising: (1) a fifth gate coupled to the second node; and (2) a fifth channel, the fourth channel and the fifth channel being sequentially coupled in series between the first potential and the fourth node so that in operation the output voltage is provided at the fourth node.

Claim 13

The integrated circuit of claim 10 wherein coupling is by direct connection.

Claim 14

The integrated circuit of claim 10 wherein the first potential is more positive than the second potential.

Claim 15

The integrated circuit of claim 10 wherein the second potential is more positive than the first potential.

Claim 16

The integrated circuit of claim 10 wherein one of the set consisting of the first potential and the second potential is ground.

Claim 17

The integrated circuit of claim 10 further comprising a sixth field effect transistor comprising a channel coupled in series between the first node and the third node.

Claim 18

The integrated circuit of claim 15 wherein coupling is by direct connection.

Claim 19

The integrated circuit of claim 10 further comprising: a. a seventh field effect transistor comprising: (1) a seventh channel coupled in series between the third channel and the second potential; and (2) a seventh gate; and b. an eighth field effect transistor comprising: (1) an eighth gate coupled to the seventh gate; and (2) an eighth channel coupled in series between the second channel and the second potential.

Claim 20

The integrated circuit of claim 17 wherein coupling is by direct connection.

Claim 21

The integrated circuit of claim 10 wherein the first device comprises a semiconductor.

Claim 22

The integrated circuit of claim 10 wherein the second device comprises a semiconductor.

Claim 23

A circuit for providing a regulated voltage, the circuit operable between at least two supply rails, the circuit comprising: a. a circuit for providing a reference voltage; b. a first branch for conducting a first current between the supply rails, and for establishing a first voltage responsive to the first current, the first branch comprising: (1) means for limiting the first current; (2) a first node characterized by the first voltage; and (3) a first transistor,.coupled to the first node and responsive to the reference voltage, for further limiting the first current; c. a second branch for conducting a second current between the supply rails, and for establishing a second voltage responsive to the second current, the second branch comprising: (1) a second transistor responsive to the first voltage; and (2) a second node characterized by the second voltage; d. a circuit for controlling the second current so that it mirrors the first current; and e. a third branch for conducting a third current between the supply rails, the third branch comprising: (1) a third transistor for limiting the third current in response to the first voltage; (2) a fourth transistor for further limiting the third current in response to the second voltage; and (3) a load for establishing the output voltage in response to the third current.

Claim 24

A circuit for providing a regulated voltage, the circuit operable between at least two supply rails, the circuit comprising: a. a circuit for providing a reference voltage; b. a first branch for conducting a first current between the supply rails, and for establishing a first voltage responsive to the first current, the first branch comprising: (1) means for limiting the first current; (2) a first node characterized by the first voltage; and (3) a first transistor,.coupled to the first node and responsive to the reference voltage, for further limiting the first current; c. a second branch for conducting a second current between the supply rails, and for establishing a second voltage responsive to the second current, the second branch comprising: (1) a second transistor responsive to the first voltage; and (2) a second node characterized by the second voltage; d. a circuit for controlling the second current so that it mirrors the first current; and e. a third branch for conducting a third current between the supply rails, the third branch comprising: (1) a third transistor for limiting the third current in response to the first voltage; (2) a fourth transistor for further limiting the third current in response to the second voltage; and (3) a load for establishing the output voltage in response to the third current.

Claim 25

The circuit of claim 21 wherein the means for limiting the first current comprises a resistor.

Claim 26

The circuit of claim 21 wherein the means for limiting the first current comprises a semiconductor.

Claim 27

The circuit of claim 21 wherein the first, the second, the third, and the fourth transistors each comprise a field effect transistor.

Claim 28

The circuit of claim 21 wherein the circuit for controlling the second current comprises at least two field effect transistors coupled to form a current mirror circuit.

Claim 29

The circuit of claim 21 wherein the circuit for controlling the second current comprises at least four field effect transistors coupled to form a first current mirror in series with a second current mirror.

Claim 30

The circuit of claim 21 wherein the load comprises a resistor.

Claim 31

The circuit of claim 21 wherein the load comprises a semiconductor.