Patent US5482880A successfully refreshed from Google Patents.
US5482880A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory cell and fabrication method
Assignee: Texas Instruments Inc
•
Filing: 1993-05-24
•
Granted: 1996-01-09
•
Expires: 2013-05-24
Abstract
Abstract In one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.
Inventors
- 👤 Cetin Kaya
- 👤 David Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:51
CPC Classifications
H; H10; H10B; H10B41/00; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
110 words
A method of forming a non-volatile memory cell structure comprising the steps of: forming a floating gate over and insulated from channel region disposed in a semiconductor region; forming a control gate over and insulated from said floating gate; implanting heavily doped source and drain regions within said semiconductor region and abutting a surface thereof, said source and drain regions separated by said channel region; implanting a lightly doped region in said channel region at least partially beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said substrate, said lightly doped region being less lightly doped than said heavily doped regions.
Claim 2
Independent Claim
110 words
A method of forming a non-volatile memory cell structure comprising the steps of: forming a floating gate over and insulated from channel region disposed in a semiconductor region; forming a control gate over and insulated from said floating gate; implanting heavily doped source and drain regions within said semiconductor region and abutting a surface thereof, said source and drain regions separated by said channel region; implanting a lightly doped region in said channel region at least partially beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said substrate, said lightly doped region being less lightly doped than said heavily doped regions.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein said source and drain regions and said lightly doped region comprise n-doped silicon and said channel region comprises p-doped silicon.
Claim 4
Dependent Claim
17 words
The method of claim 2 wherein said source and drain regions are formed by doping with arsenic.
Claim 5
Dependent Claim
17 words
The method of claim 2 wherein said source and drain regions are formed by doping with phosphorus.
Claim 6
Dependent Claim
23 words
The method of claim 2 wherein said lightly doped region is doped to between about 10 13 and 10 14 cm -2 .
Claim 7
Dependent Claim
38 words
The method of claim 2 and further comprising the step of forming a pocket region of conductivity type opposite that of said source and drain regions, said pocket region formed between said source region and said channel region.
Claim 8
Dependent Claim
18 words
The method of claim 1 wherein said step of forming a lightly doped region comprises doping with phosphorus.
Claim 9
Dependent Claim
19 words
The method of claim 7 wherein said step of forming a lightly doped regions further comprises doping with arsenic.
Claim 10
Dependent Claim
18 words
The method of claim 1 wherein said step of forming a lightly doped region comprises doping with arsenic.
Claim 11
Dependent Claim
18 words
The method of claim 1 wherein said floating gate and said control gate are formed by depositing polysilicon.
Claim 12
Dependent Claim
30 words
The method of claim 1 wherein said floating gate is insulated from said channel by an oxide and control gate is insulated from said floating gate by an oxide/nitride/oxide layer.
Claim 13
Dependent Claim
24 words
The method of claim 1 wherein said lightly dotted region is formed by implanting phosphorus with an energy of about 100 to 200 keV.
Claim 14
Dependent Claim
24 words
The method of claim 1 wherein said lightly doped region is formed by implanting arsenic with an energy of about 200 to 400 keV.
Claim 15
Independent Claim
109 words
A method of forming a non-volatile memory cell structure comprising the steps of: forming heavily doped source and drain regions within a semiconductor region and abutting a surface thereof, said source and drain regions separated by a channel region; forming a floating gate over and insulated from said channel region; forming a control gate over and insulated from said floating gate; and forming a lightly doped region in said channel region beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said substrate, wherein said lightly doped region is doped to between about 10 13 and 10 14 cm -2 .
Claim 16
Independent Claim
109 words
A method of forming a non-volatile memory cell structure comprising the steps of: forming heavily doped source and drain regions within a semiconductor region and abutting a surface thereof, said source and drain regions separated by a channel region; forming a floating gate over and insulated from said channel region; forming a control gate over and insulated from said floating gate; and forming a lightly doped region in said channel region beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said substrate, wherein said lightly doped region is doped to between about 10 13 and 10 14 cm -2 .
References Cited (Backward Citations)
JPS5315772A
Cited
US4288256A
Cited
FR2464536A1
Cited
JPS57102073A
Cited
US5098855A
Cited
JPS60247974A
Cited
EP0197501A2
Cited
US4804637A
Cited
EP0273728A2
Cited
EP0360504A2
Cited
US5019527A
Cited
JPH03156975A
Cited
EP0513923A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |