US5482884A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-temperature process metal-to-metal antifuse employing silicon link
Assignee: Microsemi SoC Corp
•
Filing: 1994-08-09
•
Granted: 1996-01-09
•
Expires: 2014-08-09
Abstract
Abstract A process for fabricating the metal-to-metal antifuse of the present invention includes the steps of forming a first metal layer on a semiconductor or other microcircuit structure; forming a first barrier layer over the first metal layer; forming a thick insulating layer over the barrier layer; forming an antifuse aperture in the thick insulating layer; forming a first heavily doped amorphous silicon layer in the aperture over the first barrier layer; forming a dielectric antifuse material layer over the first amorphous silicon layer; forming a second heavily doped amorphous silicon layer over the first dielectric antifuse material layer; forming a second barrier layer over the second amorphous silicon layer; and forming a second metal layer over the second barrier layer.
Inventors
- 👤 John L. McCollum
- 👤 Abdul R. Forouhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:05
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; Y; Y10; Y10S; Y10S148/00; Y10S148/055
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
148 words
A process for fabricating a metal-to-metal antifuse on an insulating layer disposed on a semiconductor or other microcircuit structure including the steps of: forming a first metal layer on said insulating layer; forming a lower barrier layer over said first metal layer; forming a first heavily-doped amorphous silicon layer over said lower barrier layer; forming an inter-metal dielectric layer over said first heavily-doped amorphous silicon layer; forming an antifuse aperture in said inter-metal dielectric layer to expose a portion of an upper surface of said first heavily-doped amorphous silicon layer; forming a dielectric antifuse layer over said portion of said upper surface of said first heavily-doped amorphous silicon layer in said antifuse aperture; forming a second heavily-doped amorphous silicon layer over said dielectric antifuse layer; forming an upper barrier layer over said second heavily-doped amorphous silicon layer; and forming a second metal layer over said upper barrier layer.
Claim 2
Dependent Claim
148 words
A process for fabricating a metal-to-metal antifuse on an insulating layer disposed on a semiconductor or other microcircuit structure including the steps of: forming a first metal layer on said insulating layer; forming a lower barrier layer over said first metal layer; forming a first heavily-doped amorphous silicon layer over said lower barrier layer; forming an inter-metal dielectric layer over said first heavily-doped amorphous silicon layer; forming an antifuse aperture in said inter-metal dielectric layer to expose a portion of an upper surface of said first heavily-doped amorphous silicon layer; forming a dielectric antifuse layer over said portion of said upper surface of said first heavily-doped amorphous silicon layer in said antifuse aperture; forming a second heavily-doped amorphous silicon layer over said dielectric antifuse layer; forming an upper barrier layer over said second heavily-doped amorphous silicon layer; and forming a second metal layer over said upper barrier layer.
Claim 3
Dependent Claim
144 words
A process for fabricating a metal-to-metal antifuse on an insulating layer disposed on a semiconductor or other microcircuit structure including the steps of: forming a first metal layer on said insulating layer; forming a lower barrier layer over said first metal layer; forming an inter-metal dielectric layer over said lower barrier layer; forming an antifuse aperture in said inter-metal dielectric layer to expose a portion of an upper surface of said lower barrier layer; forming a first heavily-doped amorphous silicon layer over said portion of said upper surface of said lower barrier layer in said antifuse aperture; forming a dielectric antifuse layer over said first heavily-doped amorphous silicon layer; forming a second heavily-doped amorphous silicon layer over said dielectric antifuse layer; forming an upper barrier layer over said second heavily-doped amorphous silicon layer; and forming a second metal layer over said upper barrier layer.
Claim 4
Dependent Claim
144 words
A process for fabricating a metal-to-metal antifuse on an insulating layer disposed on a semiconductor or other microcircuit structure including the steps of: forming a first metal layer on said insulating layer; forming a lower barrier layer over said first metal layer; forming an inter-metal dielectric layer over said lower barrier layer; forming an antifuse aperture in said inter-metal dielectric layer to expose a portion of an upper surface of said lower barrier layer; forming a first heavily-doped amorphous silicon layer over said portion of said upper surface of said lower barrier layer in said antifuse aperture; forming a dielectric antifuse layer over said first heavily-doped amorphous silicon layer; forming a second heavily-doped amorphous silicon layer over said dielectric antifuse layer; forming an upper barrier layer over said second heavily-doped amorphous silicon layer; and forming a second metal layer over said upper barrier layer.
References Cited (Backward Citations)
US4847732A
Cited
US4796075A
Cited
US4651409A
Cited
US4870302A
Cited
WO1987000969A1
Cited
US4748490A
Cited
WO1987002827A1
Cited
US5134457A
Cited
US4899205A
Cited
US4943538A
Cited
US5266829A
Cited
US4822753A
Cited
US4933576A
Cited
US4914055A
Cited
US5272101A
Cited
US5411917A
Cited
US5070384A
Cited
EP0455414A1
Cited
US5194759A
Cited
US5095362A
Cited
WO1992013359A1
Cited
US5166556A
Cited
US5100827A
Cited
US5322812A
Cited
US5196724A
Cited
US5233217A
Cited
WO1992020109A1
Cited
US5290734A
Cited
US5120679A
Cited
WO1993003499A1
Cited
US5272666A
Cited
US5171715A
Cited
US5381035A
Cited
US5308795A
Cited
US5300456A
Cited
US5369054A
Cited
US5440167A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |