Fast pipelined 2-D discrete cosine transform architecture

Claim 2

A DCT circuit comprising: a pre-processor stage receiving each element x ij i,j=1,2,. . . ,N, where N is an integer≧4, of an input matrix X, said pre-processor stage simultaneously outputting Q sequences of one or more columns of elements of a matrix A f having elements a ij =x ij +x.sub.(N-i+1)j i=1,2, . . . N/2, j=1,2, . . . , and Q≧1 of one or more sequences columns of elements of a matrix A r having elements a ij =x.sub.(i-N/2)j -x.sub.(3N/2-i+1)j i=N/2+1, N/2+2, . . . ,N, j=1,2, . . . ,N, where Q is an integer≧1, and a 1-D DCT processing stage simultaneously receiving each of said 2Q sequences of one or more vectors of elements of said matrices A f and A r , P sequences of one or more rows of elements of an N/2×N/2 DCT cosine coefficient matrix C 1 and P sequences of rows of elements of an N/2×N/2 DCT cosine coefficient matrix C 2 , where P is an integer≧1, said 1-D DCT processing stage comprising K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix Y o comprising elements y ij i=1,3, . . . ,N, j=1,2, . . . ,N, where K is an integer≧1 and where ##EQU16## and K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix Y e comprising elements y ij i=2,4, . . . ,N, j=1,2, . . . ,N, where ##EQU17## wherein said integers Q, P and K are selected independently of said integer N, and wherein said integers K, P, and Q are selected to balance a processing speed of said 1-D DCT circuit against an area occupied by said 1-D DCT circuit.

Claim 3

The circuit of claim 1 wherein said 1-D DCT stage comprises a plurality of column register circuits, wherein each of said 2Q sequences of one or more columns of elements of said matrices A f and A r are received in column circuits of a first type and wherein each of said 2P sequences of one or more rows of elements of said matrices C 1 and C 2 are received in column circuits of a different type than said first type.

Claim 4

The circuit of claim 2 wherein each column register circuit comprises a plurality of serially connected registers for receiving one matrix element per clock cycle at a first one of said registers and for sequentially shifting said inputted matrix elements from register to register on each successive clock cycle.

Claim 5

The circuit of claim 3 wherein each column multiplication circuit comprises a plurality of sequentially connected processing elements, a first one of said processing elements receiving one matrix element per cycle, and outputting each of said received elements and a partial product of each received matrix element multiplied with a corresponding matrix element received in a first register of an associated column register circuit, each other processing element capable of receiving each of said matrix elements and said corresponding partial product from a previous processing element, one matrix element and partial product per cycle, said other processing elements also capable of performing part of a multiplication of said received matrix element and a matrix element received in a corresponding register of said associated column register and modifying said received partial product depending on said performed portion of said multiplication.

Claim 6

The circuit of claim 1 wherein each of said 2Q sequences outputted by said pre-processor stage comprises N/K repetitions of each column of elements comprised in each of said 2Q sequences.

Claim 7

The circuit of claim 1 wherein said 1-DCT stage utilizes N 3 /2K clocks for receiving each element of said 2Q sequences of elements.

Claim 8

The circuit of claim 1 wherein said integers Q and P are selected so that 2Q and 2P are powers of 2.

Claim 9

The circuit of claim 1 wherein said pre-processing circuit comprises: first and second ring registers, each comprising N/2 registers linked via inputs and outputs thereof to form a ring register, an output of one of said N/2 registers serving as an output of said ring register, said first ring register receiving the elements in the first N/2 rows of each column of said matrix X and said second ring register receiving the elements in the last N/2 rows of each column of said matrix X, in reverse order, wherein each ring register successively outputs each received element at least once, an addition circuit for adding each matrix element outputted by said first ring register with a corresponding element outputted by said second ring register, and a subtraction circuit for subtracting each matrix element outputted from said second ring register from a corresponding matrix element outputted from said first ring register.

Claim 10

The DCT circuit of claim 1 further comprising: a transpose memory receiving said matrices Y o and Y e and outputting a transpose matrix Y t having elements y ij t =y ji of said matrices Y e and Y o , a second pre-processor stage receiving each element of said matrix Y t , said pre-processor stage simultaneously outputting Q sequences of one or more columns of elements of a matrix A' f having elements a' ij =y ij t +y.sub.(N-i+1)j t i=1,2, . . . ,N/2, j=1,2,. . . ,N, and Q sequences of one or more columns of elements to a matrix A' r having elements a' ij =y ij t -y.sub.(i-N/2)j t i=N/2+1, N/2+2, . . . ,N, j=1,2, . . . ,N, and a second 1-D DCT processing stage simultaneously receiving each of said 2Q sequences of one or more columns of elements of said matrices A' f and A' r outputted by said second pre-processor stage, P sequences of one or more rows of elements of said matrix C 1 and P sequences of rows of elements of said matrix C 2 , said second 1-D DCT processing stage comprising K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix Z o comprising elements z ij i=1,3, . . . ,N, j=1,2, . . . ,N, where ##EQU18## and K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix Z e comprising elements z ij i=2,4, . . . ,N, j=1,2, . . . ,N, where ##EQU19##

Claim 11

An IDCT circuit comprising: a 1-D IDCT processing stage simultaneously receiving Q sequences of one or more columns of elements z ij i=1,3, . . . N, j=1,2, . . . , N, where N is an integer≧4 of a matrix Z o , where Q is an integer≧1, Q sequences of one or more columns of elements z ij i=2,4, . . . ,N, j=1,2, . . . ,N, of a matrix Z e , P sequences of one or more rows of elements of an N/2×N/2 IDCT cosine coefficient matrix C 1 t , where P is an integer≧1, and P sequences of rows of elements of an N/2×N/2 DCT cosine coefficient matrix C 2 t said 1-D IDCT processing stage comprising K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix R comprising elements r ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, for a total of K sequences of one or more vectors of said matrix R, where K is an integer≧1 and where ##EQU20## and K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix T comprising elements t ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, for a total of K sequences of one or more vectors of said matrix T, where ##EQU21## and wherein said integers Q, P and K are selected independently of said integer N, and wherein said integers Q, P and K are selected to balance a processing speed of said 1-D IDCT circuit against an area occupied by said 1-D IDCT circuit, a post-processing stage for receiving said 2K sequences of one or more vectors of said matrices R and T and for outputting elements of a matrix Y f having elements y ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, where y ij =r+t ij and elements of a matrix Y r having elements y ij i=N/2+1, N/2+2, . . . ,N, j=1,2, . . . ,N, where y ij =r.sub.(i-N/2)j -t.sub.(i-N/2)j.

Claim 12

An IDCT circuit comprising: a 1-D IDCT processing stage simultaneously receiving Q sequences of one or more columns of elements z ij i=1,3, . . . N, j=1,2, . . . , N, where N is an integer≧4 of a matrix Z o , where Q is an integer≧1, Q sequences of one or more columns of elements z ij i=2,4, . . . ,N, j=1,2, . . . ,N, of a matrix Z e , P sequences of one or more rows of elements of an N/2×N/2 IDCT cosine coefficient matrix C 1 t , where P is an integer≧1, and P sequences of rows of elements of an N/2×N/2 DCT cosine coefficient matrix C 2 t said 1-D IDCT processing stage comprising K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix R comprising elements r ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, for a total of K sequences of one or more vectors of said matrix R, where K is an integer≧1 and where ##EQU20## and K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix T comprising elements t ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, for a total of K sequences of one or more vectors of said matrix T, where ##EQU21## and wherein said integers Q, P and K are selected independently of said integer N, and wherein said integers Q, P and K are selected to balance a processing speed of said 1-D IDCT circuit against an area occupied by said 1-D IDCT circuit, a post-processing stage for receiving said 2K sequences of one or more vectors of said matrices R and T and for outputting elements of a matrix Y f having elements y ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, where y ij =r+t ij and elements of a matrix Y r having elements y ij i=N/2+1, N/2+2, . . . ,N, j=1,2, . . . ,N, where y ij =r.sub.(i-N/2)j -t.sub.(i-N/2)j.

Claim 13

The IDCT circuit of claim 10 wherein said post-processing circuit comprises: a first group of K parallel registers for receiving each element of a corresponding one of said K sequences of one or more vectors of elements of said matrix R, a second group of K parallel registers for receiving each element of a corresponding one of said K sequences of one or more vectors of elements of said matrix T, a first multiplexer for alternately selecting each element stored in each register of said first group of K registers, a second multiplexer for alternately selecting each [value] element stored in each register of said second group of K registers, an addition circuit for adding together said elements alternately selected by said first and second multiplexers, and a subtraction circuit for subtracting said elements alternately selected by said first multiplexer from said element selected by said second multiplexer.

Claim 14

The IDCT circuit of claim 10 further comprising: a transpose memory receiving said matrices Y f and Y r and outputting Q sequences of one or more columns of a transpose matrix Y o t having elements y ij t i=1,3, . . . ,N, j=1,2, . . . ,N, where y ij t =y ji of said matrices Y f and Y r , and Q sequences of one or more columns of a transpose matrix Y e t having elements y ij t i=2,4, . . . ,N, j=1,2, . . . ,N, where y ij t =y ji of said matrices Y f and Y r , a second 1-D IDCT processing stage simultaneously receiving said 2Q sequences of one or more columns of elements of said matrices Y o t and Y e t , P sequences of one or more rows of elements of said IDCT cosine coefficient matrix C 1 t and P sequences of rows of elements of said DCT cosine coefficient matrix C 2 t , said second 1-D IDCT processing stage comprising K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix R' comprising elements r' ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, for a total of K sequences of one or more vectors said matrix R', where ##EQU22## and K column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix T' comprising elements t' ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, for a total of K sequences of one or more vectors of said matrix T', where ##EQU23## a second post-processing stage for receiving said 2K sequences of one or more vectors of said matrices R' and T' and for outputting elements of a matrix X f having elements x ij i=1,2, . . . ,N/2, j=1,2, . . . ,N, where each x ij =r' ij +t' ij and elements of a matrix X r having elements x ij i=N/2+1, N/2+2, j=1,2, . . . ,N, where each x ij =r'.sub.(i-N/2)j -t'.sub.(i-N2)j.

Claim 15

The circuit of claim 10 wherein said post-processing circuit comprises: K addition circuits, each addition circuit receiving, in parallel, a different one of said K sequences of one or more vectors of elements of said matrix R and a different one of said K sequences of one or more vectors of elements of said matrix T and outputting a sequence of unique vectors of elements of said matrix Y f , and K subtraction circuits, each subtraction circuit receiving, in parallel, a different one of said K sequences of one or more vectors of elements of said matrix R and a different one of said K sequences of one or more vectors of elements of said matrix T and outputting a sequence of one or more unique vectors of elements of said matrix Y r .