US5490102A
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Low capacitance content-addressable memory cell
Assignee: Micron Technology Inc
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Filing: 1994-06-15
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Granted: 1996-02-06
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Expires: 2014-06-15
Abstract
Abstract A content addressable memory (CAM) comprising an array of CAM cells is disclosed. Each CAM cell includes a memory cell and a compare circuit that writes the memory cell from the bit lines if the word line is active and that compares memory cell data with an input data bit on the bit lines if the word line is inactive.
Inventors
- 👤 Farah Jubran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:50
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
187 words
A content addressable memory cell, comprising: memory cell for storing a data bit; compare circuit coupled to a pair of bit lines and a word line, the compare circuit coupled to write the data bit from the bit lines if the word line is active, the compare circuit coupled to compare the data bit with an input data bit on the bit lines if the word line is inactive; discharge transistor including a gate coupled to the compare circuit at a match node such that the compare circuit switches on the discharge transistor if the data bit mismatches the input data bit, the discharge transistor coupled to discharge the match line if the compare circuit senses a mismatch between the data bit and the input data bit; write control transistor coupled to the match node and to the word line, the write control transistor switching off the discharge transistor if the word line is active; disable circuit coupled to the match node and coupled to a disable line for the memory cell, the disable circuit disabling the compare circuit according to a signal on the disable line.
Claim 2
Dependent Claim
187 words
A content addressable memory cell, comprising: memory cell for storing a data bit; compare circuit coupled to a pair of bit lines and a word line, the compare circuit coupled to write the data bit from the bit lines if the word line is active, the compare circuit coupled to compare the data bit with an input data bit on the bit lines if the word line is inactive; discharge transistor including a gate coupled to the compare circuit at a match node such that the compare circuit switches on the discharge transistor if the data bit mismatches the input data bit, the discharge transistor coupled to discharge the match line if the compare circuit senses a mismatch between the data bit and the input data bit; write control transistor coupled to the match node and to the word line, the write control transistor switching off the discharge transistor if the word line is active; disable circuit coupled to the match node and coupled to a disable line for the memory cell, the disable circuit disabling the compare circuit according to a signal on the disable line.
Claim 3
Dependent Claim
27 words
The content addressable memory cell of claim 1, wherein the disable circuit disables the compare circuit by discharging the match node when both bit lines are low.
Claim 4
Dependent Claim
205 words
A content addressable memory, comprising an array of content addressable memory (cam) cells for storing an array of data bits, each cam cell comprising a compare circuit coupled to write a corresponding data bit in the array from a set of bit lines if a word line is active, the compare circuit coupled to compare the corresponding data bit with an input data bit on the bit lines if the word line is inactive, each cam cell further comprising a discharge transistor coupled to discharge the match line if the compare circuit senses a mismatch between the data bit and the input data bit wherein a gate of the discharge transistor is coupled to the compare circuit at a match node to switch on the discharge transistor if the data bit mismatches the input data bit, the content addressable memory further comprising a write control transistor coupled to the match node and to the word line, the write control transistor switching off the discharge transistor if the word line is active and a disable circuit coupled to the match node and coupled to a disable line for the memory cell, the disable circuit disabling the compare circuit according to a signal on the disable line.
Claim 5
Dependent Claim
205 words
A content addressable memory, comprising an array of content addressable memory (cam) cells for storing an array of data bits, each cam cell comprising a compare circuit coupled to write a corresponding data bit in the array from a set of bit lines if a word line is active, the compare circuit coupled to compare the corresponding data bit with an input data bit on the bit lines if the word line is inactive, each cam cell further comprising a discharge transistor coupled to discharge the match line if the compare circuit senses a mismatch between the data bit and the input data bit wherein a gate of the discharge transistor is coupled to the compare circuit at a match node to switch on the discharge transistor if the data bit mismatches the input data bit, the content addressable memory further comprising a write control transistor coupled to the match node and to the word line, the write control transistor switching off the discharge transistor if the word line is active and a disable circuit coupled to the match node and coupled to a disable line for the memory cell, the disable circuit disabling the compare circuit according to a signal on the disable line.
Claim 6
Dependent Claim
26 words
The content addressable memory of claim 3, wherein the disable circuit disables the compare circuit by discharging the match node when both bit lines are low.
Claim 7
Independent Claim
140 words
A method for accessing a memory cell, comprising the steps of: writing a data bit from a set of bit lines for the memory cell if a word line for the memory cell is active; comparing the data bit with an input data bit on the bit lines if the word line is inactive including the step of comparing the data bit with the input data bit on the bit lines while the word line is inactive; discharging a match line if the data bit mismatches the input data bit including the step of switching on a discharge transistor coupled to the match line if the data bit mismatches the input data bit; switching off the discharge transistor if the word line is active; disabling the comparing step according to a signal on an enable line for the memory cell.
Claim 8
Independent Claim
140 words
A method for accessing a memory cell, comprising the steps of: writing a data bit from a set of bit lines for the memory cell if a word line for the memory cell is active; comparing the data bit with an input data bit on the bit lines if the word line is inactive including the step of comparing the data bit with the input data bit on the bit lines while the word line is inactive; discharging a match line if the data bit mismatches the input data bit including the step of switching on a discharge transistor coupled to the match line if the data bit mismatches the input data bit; switching off the discharge transistor if the word line is active; disabling the comparing step according to a signal on an enable line for the memory cell.
Claim 9
Dependent Claim
39 words
The method of claim 5, wherein the step of disabling the comparing step according to a signal on an enable line for the memory cell comprises the step of discharging the match node when both bit lines are low.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |