Non-volatile semiconductor memory device having disturb verify function

Claim 2

An electrically writable nonvolatile semiconductor memory device comprising: a plurality of electrically writable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; detecting means for detecting a change of the threshold voltage of each of said non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing said selected memory cell; and restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value of the threshold voltage of the non-selected memory cell before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell.

Claim 3

A semiconductor memory device according to claim 1, wherein said detecting means provides a number of detection levels for detecting the threshold voltage of the selected memory cell more than a minimum number of the detection levels necessary for reading information stored in the selected memory cell and compares said detection levels with the threshold voltage of each of the memory cells thereby to obtain information for detecting the change of the threshold voltage in addition to the information stored in the selected memory cell.

Claim 4

A semiconductor memory device according to claim 1, further comprising a control circuit for causing said detecting means to operate, when a writing mode is specified by an external signal or command, after writing into said selected memory and causing said restoring means to operate based on a result of detection of the change of the threshold voltage of the non-selected memory cell.

Claim 5

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable and erasable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; detecting means for detecting a change of a threshold voltage of each of said non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing or erasing said selected memory cell; and restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell, wherein said detecting means provides a number of detection levels for detecting the threshold voltage of the non-selected memory cell more than a minimum number of the detection levels necessary for reading information stored in the memory cell and compares the detection levels with the threshold voltage of each memory cell thereby to derive information on the change of the threshold voltage in addition to information stored in the memory cell.

Claim 6

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable and erasable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; detecting means for detecting a change of a threshold voltage of each of said non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing or erasing said selected memory cell; and restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell, wherein said detecting means provides a number of detection levels for detecting the threshold voltage of the non-selected memory cell more than a minimum number of the detection levels necessary for reading information stored in the memory cell and compares the detection levels with the threshold voltage of each memory cell thereby to derive information on the change of the threshold voltage in addition to information stored in the memory cell.

Claim 7

A semiconductor memory device according to claim 4, further comprising a control circuit for causing said detecting means to operate, when a writing mode or an erasing mode is specified by an external signal or command, after writing or erasing said selected memory cell and causing said restoring means to operate based on a result of detecting the change of the threshold voltage of the non-selected memory cell.

Claim 8

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; first detecting means for detecting a change of a threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing said selected memory cell; second detecting means for detecting a change of the threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when erasing said selected memory cell; and restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell by said first or second detecting means, wherein each of said first and second detecting means provides a number of detection levels for detecting the threshold voltage of the selected memory cell more than a minimum number of the detection levels necessary for reading information stored in said selected memory cell and compares said detection levels with the threshold voltage of the selected memory cell thereby to obtain information for detecting the change of the threshold voltage in addition to information stored in the memory cell.

Claim 9

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; first detecting means for detecting a change of a threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing said selected memory cell; second detecting means for detecting a change of the threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when erasing said selected memory cell; and restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell by said first or second detecting means, wherein each of said first and second detecting means provides a number of detection levels for detecting the threshold voltage of the selected memory cell more than a minimum number of the detection levels necessary for reading information stored in said selected memory cell and compares said detection levels with the threshold voltage of the selected memory cell thereby to obtain information for detecting the change of the threshold voltage in addition to information stored in the memory cell.

Claim 10

A semiconductor memory device according to claim 6, wherein each of said first and second detecting means provides a plurality of threshold voltage detection levels, of which a number is at least twice a minimum number necessary for reading information stored in said memory cell when obtaining information as to whether the threshold voltage of the non-selected memory cell has changed or not from its original value at the time of writing or erasing and provides a plurality of threshold voltage detection levels, of which a number is at least three times a minimum number necessary for reading information stored in the memory cell when obtaining information as to whether the threshold voltage of the nonselected memory cell has changed up or down from its original value at the time of writing or erasing, and compares said detection levels with the threshold voltage of the non-selected memory cell to obtain information for detecting the change of the threshold voltage of said non-selected memory cell in addition to information stored in the selected memory cell.

Claim 11

An electrically writable nonvolatile semiconductor memory device comprising: a plurality of electrically writable nonvolatile semiconductor memory cells arranged in rows and columns: a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder; reading means for reading said memory cell in the selected state through said decoder circuit; detecting means for detecting a change of a threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing said selected memory cell; restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell; and counting means provided for each block including one or a plurality of the memory cells for counting a number of times of selection by which the block is selected for writing, wherein only when the number of times of selection exceeds a predetermined value, said change of the threshold voltage of the memory cell in said block is detected and the threshold voltage is restored.

Claim 12

An electrically writable nonvolatile semiconductor memory device comprising: a plurality of electrically writable nonvolatile semiconductor memory cells arranged in rows and columns: a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder; reading means for reading said memory cell in the selected state through said decoder circuit; detecting means for detecting a change of a threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing said selected memory cell; restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell; and counting means provided for each block including one or a plurality of the memory cells for counting a number of times of selection by which the block is selected for writing, wherein only when the number of times of selection exceeds a predetermined value, said change of the threshold voltage of the memory cell in said block is detected and the threshold voltage is restored.

Claim 13

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable and erasable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; detecting means for detecting a change of a threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when erasing said selected memory cell; restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the threshold voltage of the non-selected memory cell; and counting means provided for each block including one or a plurality of said memory cells for counting a number of times of selection by which the block is selected for writing or erasing, wherein only when said number of times of selection exceeds a predetermined value, the change of the threshold voltage of the memory cell in said block is detected and the threshold voltage is restored.

Claim 14

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable and erasable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; detecting means for detecting a change of a threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when erasing said selected memory cell; restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the threshold voltage of the non-selected memory cell; and counting means provided for each block including one or a plurality of said memory cells for counting a number of times of selection by which the block is selected for writing or erasing, wherein only when said number of times of selection exceeds a predetermined value, the change of the threshold voltage of the memory cell in said block is detected and the threshold voltage is restored.

Claim 15

A semiconductor memory device according to claim 8, further comprising a control circuit for reading count information from said counting means when a mode for detecting the change of the threshold voltage of the non-selected memory cell and restoring the threshold voltage is selected by an external signal or external command, and for activating said detecting means when the number of times of selection exceeds the predetermined value, and when the change of the threshold voltage of the non-selected memory cell is detected, activating said restoring means.

Claim 16

A semiconductor memory device according to claim 8, wherein said detecting means provides a number of detection levels more than a minimum number thereof necessary for reading information stored in the memory cell and compares said detection levels with the threshold voltage of the memory cell to derive information stored in said memory cell and information on the change of the threshold voltage.

Claim 17

A semiconductor memory device according to claim 8, wherein said detecting means provides a plurality of threshold voltage detection levels, of which a number is at least twice a minimum number necessary for reading information stored in said memory cell when obtaining information as to whether the threshold voltage of the non-selected memory cell has changed or not by comparing its original value with the detection levels at the time of writing or erasing or a plurality of threshold voltage detection levels, of which a number is at least three times a minimum number necessary for reading information stored in said memory cell when obtaining information as to whether the threshold voltage of the non-selected memory cell has changed up or down by comparing its original value with the detection levels at the time of writing or erasing, and compares said detection levels with the threshold voltage of the non-selected memory cell to obtain information stored in said selected memory cell and information on said change of the threshold voltage of the non-selected memory cell.

Claim 18

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; first detecting means for detecting a change of the threshold voltage of the non-selected memory cell, which change is caused by a voltage applied to the non-selected memory cell when writing said selected memory cell; second detecting means for detecting the change of the threshold voltage of said non-selected memory cell which change is caused by a voltage applied to said non-selected memory cell, when erasing said selected memory cell; restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell; and counting means provided for each block including one or a plurality of said memory cells for counting a number of times of selection by which the block is selected for writing or erasing, wherein only when the number of times of selection exceeds a predetermined value, the change of the threshold voltage of the memory cell in said block is detected and the threshold voltage is restored.

Claim 19

An electrically writable and erasable nonvolatile semiconductor memory device comprising: a plurality of electrically writable nonvolatile semiconductor memory cells arranged in rows and columns; a decoder circuit for making at least one of said memory cells in a selected state and the other ones in a non-selected state; writing means for writing said memory cell in the selected state through said decoder circuit; erasing means for erasing said memory cell in the selected state through said decoder circuit; reading means for reading said memory cell in the selected state through said decoder circuit; first detecting means for detecting a change of the threshold voltage of the non-selected memory cell, which change is caused by a voltage applied to the non-selected memory cell when writing said selected memory cell; second detecting means for detecting the change of the threshold voltage of said non-selected memory cell which change is caused by a voltage applied to said non-selected memory cell, when erasing said selected memory cell; restoring means for restoring the threshold voltage of the non-selected memory cell to a value equal to or near to its original value before its change on the basis of a result of detecting the change of the threshold voltage of the non-selected memory cell; and counting means provided for each block including one or a plurality of said memory cells for counting a number of times of selection by which the block is selected for writing or erasing, wherein only when the number of times of selection exceeds a predetermined value, the change of the threshold voltage of the memory cell in said block is detected and the threshold voltage is restored.

Claim 20

A semiconductor memory device according to claim 13, further comprising a control circuit for reading count information from said counting means when a mode for detecting the change of the threshold voltage of the non-selected memory cell and restoring the threshold voltage is selected by an external signal or an external command, and for activating said first or second detecting means if the number of times of selection exceeds a predetermined value, and activating said restoring means if the change of the threshold voltage of the non-selected memory cell is detected.

Claim 21

A semiconductor memory device according to claim 13, wherein each of said first and second detecting means provides a number of detection levels more than a minimum number thereof necessary for reading information stored in said memory cell and compares said detection levels with the threshold voltage of the memory cell to obtain information stored in said memory cell and information on the change of said threshold voltage.

Claim 22

A semiconductor memory device according to claim 13, wherein each of said first and second detecting means provides a plurality of detection levels, of which a number is at least twice a minimum number thereof necessary for reading information stored in said memory cell when obtaining information as to whether the threshold voltage of the non-selected memory cell have changed or not at the time of writing or erasing or a plurality of detection levels of which a number is at least three times a minimum number thereof necessary for reading information stored in said memory cell when obtaining information as to whether the threshold voltage of the non-selected memory cell has changed up or down at the time of writing or erasing, and compares said detection levels with the threshold voltage of each memory cell to obtain information stored in the memory cell and information on the change of the threshold voltage of the memory cell.