Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells

Claim 1

An EEPROM having a plurality of memory cells, each memory cell having a control gate, a drain electrode, and a source electrode, wherein a selected one of said plurality of memory cells has its control gate connected to a word line, its source electrode connected to a first bit line, and its drain electrode connected to a second bit line, said selected one memory cell being accessed by providing appropriate voltages to said word line, said first bit line, and said second bit line, and wherein said selected one memory cell draws through said second bit line, a first current, if said selected one memory cell is in an unprogrammed state, or a second current less than said first current, if said selected one memory cell is in a programmed state, said EEPROM including a sense amplifier, connected to a current source providing a reference current, said sense amplifier comprising: a first circuit connected to a voltage supply and said current source, and selectably connected to said second bit line through a first node, said first circuit providing a first circuit current to said first node, not to exceed said reference current, in response to a cell current being drawn through said second bit line by said selected one memory cell when a programming voltage is applied to said second bit line; and a second circuit connected to said voltage supply and said first node, said second circuit automatically providing an additional current to said first node when said cell current being drawn through said second bit line by said selected one memory cell is greater than said reference current; wherein said reference current is greater than said second current and less than said first current, and said voltage supply provides a voltage greater than said programming voltage being applied to said second bit line when programming said selected one memory cell.