Video graphics display system with adapter for display management based upon plural memory sources

Claim 2

A display adapter for connection between a host processor and a display unit of a data processing apparatus to provide management of the display unit in response to control signals from the host processor, said display adapter comprising: a graphics processor adapted to be connected to the host processor; a video memory having at least first and second dedicated memory parts, the first memory part of said video memory being adapted to be connected to the display unit; said graphics processor being responsive to a software application and being connected to the first memory part for providing display data thereto; a logic based hardware sub-system adapted to be connected to the host processor; said logic based hardware sub-system being responsive to a hardware application and being connected to the second memory part for providing display data thereto; and means operably associated with said first and second memory parts for deriving graphics data to provide displays from the first and/or the second memory parts of said video memory for transmission to the display unit, said means for deriving graphics data comprising means for transferring data stored in the second memory part to the first memory part such that data originating from the second memory part is storable with data stored in the first memory part as combined memory data in the first memory part for application to the display unit under the control of said graphics processor.

Claim 3

A display adapter as set forth in claim 1, wherein said data transferring means further comprises means for merging in the first memory part of said video memory, the data stored in the first memory part of said video memory and in the second memory part of said video memory.

Claim 4

A display adapter as set forth in claim 2, wherein said data merging means comprises means for copying data from the second memory part of said video memory into the first memory part of said video memory.

Claim 5

A display adapter as set forth in claim 3, wherein said data copying means is responsive to a subroutine of said graphics processor for copying data from the second memory part of said video memory into the first memory part of said video memory.

Claim 6

A video graphics display system comprising: a host processor; a display unit; and a display adapter interposed between said host processor and said display unit and respectively connected to the output of said host processor and the input of said display unit to provide management of said display unit in response to control signals from said host processor, said display adapter including a graphics processor having an input and an output, the input of said graphics processor being connected to said host processor, and said graphics processor being responsive to a software application in operation in said host processor for generating display data at the output of said graphics processor, a video memory having at least first and second dedicated memory parts, the first memory part of said video memory being connected to the output of said graphics processor, said video memory having an output connected to the input of said display unit, a logic based hardware sub-system having an input and an output, the input of said logic based hardware sub-system being connected to said host processor, said logic based hardware subsystem being responsive to a hardware application for generating display data at the output of said logic based hardware sub-system and having its output connected to the second memory part of said video memory, and means operably associated with said first and second memory parts for deriving graphics data to provide displays from the first and/or the second memory parts of said video memory for transmission to said display unit, said means for deriving graphics data comprising means for transferring data stored in the second memory part to the first memory part such that data originating from the second memory part is storable with data stored in the first memory part as combined memory data in the first memory part for application to said display unit under the control of said graphics processor.

Claim 7

A video graphics display system comprising: a host processor; a display unit; and a display adapter interposed between said host processor and said display unit and respectively connected to the output of said host processor and the input of said display unit to provide management of said display unit in response to control signals from said host processor, said display adapter including a graphics processor having an input and an output, the input of said graphics processor being connected to said host processor, and said graphics processor being responsive to a software application in operation in said host processor for generating display data at the output of said graphics processor, a video memory having at least first and second dedicated memory parts, the first memory part of said video memory being connected to the output of said graphics processor, said video memory having an output connected to the input of said display unit, a logic based hardware sub-system having an input and an output, the input of said logic based hardware sub-system being connected to said host processor, said logic based hardware subsystem being responsive to a hardware application for generating display data at the output of said logic based hardware sub-system and having its output connected to the second memory part of said video memory, and means operably associated with said first and second memory parts for deriving graphics data to provide displays from the first and/or the second memory parts of said video memory for transmission to said display unit, said means for deriving graphics data comprising means for transferring data stored in the second memory part to the first memory part such that data originating from the second memory part is storable with data stored in the first memory part as combined memory data in the first memory part for application to said display unit under the control of said graphics processor.

Claim 8

A video graphics display system as set forth in claim 5, wherein said data transferring means further comprises means for merging in the first memory part of said video memory, the data stored in the first memory part of said video memory and in the second memory part of said video memory.

Claim 9

A video graphics display system as set forth in claim 6, wherein said data merging means comprises means for copying data from the second memory part of said video memory into the first memory part of said video memory.

Claim 10

A video graphics display system as set forth in claim 7, wherein said data copying means is responsive to a subroutine of said graphics processor for copying data from the second memory part of said video memory into the first memory part of said video memory.

Claim 11

A display adapter for connection between a host processor and a display unit of a data processing apparatus to provide management of the display unit in response to control signals from the host processor, said display adapter comprising: a graphics processor adapted to be connected to the host processor; a video memory having at least first and second dedicated memory parts, the first part of said video memory being adapted to be connected to the display unit; said graphics processor being connected to the first memory part; a logic based hardware sub-system adapted to be connected to the host processor, said logic based hardware sub-system including a data bus interface having inputs for respectively receiving control, address and data signals from the host processor, a sequence controller, an address mapper, a data mapper, said sequence controller, said address mapper, and said data mapper being respectively connected to said data bus interface for respectively receiving control, address and data signals as provided from the output thereof, a display controller connected to the output of said sequence controller, internal registers connected to the outputs of said address and data mappers, a graphics processor/local address-data bus interface connected to the output of said display controller and having an input adapted to be connected to a local address-data bus, an access arbitration controller connected to the outputs of said address mapper and said data mapper, said access arbitration controller also being connected to an output of said graphics processor/local address-data bus interface and having first and second outputs, and a memory controller connected to the output of said graphics processor/local address-data bus interface and the first and second outputs of said access arbitration controller; said logic based hardware sub-system being connected to the second memory part; and means operably associated with said first and second memory parts for deriving graphics data to provide displays from the first and/or the second memory parts of said video memory for transmission to the display unit.

Claim 12

A display adapter for connection between a host processor and a display unit of a data processing apparatus to provide management of the display unit in response to control signals from the host processor, said display adapter comprising: a graphics processor adapted to be connected to the host processor; a video memory having at least first and second dedicated memory parts, the first part of said video memory being adapted to be connected to the display unit; said graphics processor being connected to the first memory part; a logic based hardware sub-system adapted to be connected to the host processor, said logic based hardware sub-system including a data bus interface having inputs for respectively receiving control, address and data signals from the host processor, a sequence controller, an address mapper, a data mapper, said sequence controller, said address mapper, and said data mapper being respectively connected to said data bus interface for respectively receiving control, address and data signals as provided from the output thereof, a display controller connected to the output of said sequence controller, internal registers connected to the outputs of said address and data mappers, a graphics processor/local address-data bus interface connected to the output of said display controller and having an input adapted to be connected to a local address-data bus, an access arbitration controller connected to the outputs of said address mapper and said data mapper, said access arbitration controller also being connected to an output of said graphics processor/local address-data bus interface and having first and second outputs, and a memory controller connected to the output of said graphics processor/local address-data bus interface and the first and second outputs of said access arbitration controller; said logic based hardware sub-system being connected to the second memory part; and means operably associated with said first and second memory parts for deriving graphics data to provide displays from the first and/or the second memory parts of said video memory for transmission to the display unit.

Claim 13

A display adapter as set forth in claim 9, wherein said logic based hardware sub-system comprises a video graphics array hardware sub-system.

Claim 14

A video graphics display system comprising: a host processor; a display unit; and a display adapter interposed between said host processor and said display unit and respectively connected to the output of said host processor and the input of said display unit to provide management of said display unit in response to control signals from said host processor, said display adapter including: a graphics processor connected to said host processor, a video memory having at least first and second dedicated memory parts connected to the output of said graphics processor, said video memory having an output connected to the input of said display unit, a logic based hardware sub-system connected to said host processor and having an output connected to the second memory part of said video memory, said logic based hardware sub-system of said display adapter including a data bus interface having inputs for respectively receiving control, address and data signals from said host processor, a sequence controller, an address mapper, a data mapper, said sequence controller, said address mapper, and said data mapper being respectively connected to said data bus interface for respectively receiving control, address and data signals as provided from the output thereof, a display controller connected to the output of said sequence controller, internal registers connected to the outputs of said address and data mappers, a graphics processor/local address-data bus interface connected to the output of said display controller and having an input adapted to be connected to a local address-data bus, an access arbitration controller connected to the outputs of said address mapper and said data mapper, said access arbitration controller also being connected to an output of said graphics processor/local address-data bus interface and having first and second outputs, and a memory controller connected to the output of said graphics processor/local address-data bus interface and the first and second outputs of said access arbitration controller; and means operably associated with said first and second memory parts for deriving graphics data to provide displays from the first and/or the second memory parts of said video memory for transmission to said display unit.

Claim 15

A video graphics display system comprising: a host processor; a display unit; and a display adapter interposed between said host processor and said display unit and respectively connected to the output of said host processor and the input of said display unit to provide management of said display unit in response to control signals from said host processor, said display adapter including: a graphics processor connected to said host processor, a video memory having at least first and second dedicated memory parts connected to the output of said graphics processor, said video memory having an output connected to the input of said display unit, a logic based hardware sub-system connected to said host processor and having an output connected to the second memory part of said video memory, said logic based hardware sub-system of said display adapter including a data bus interface having inputs for respectively receiving control, address and data signals from said host processor, a sequence controller, an address mapper, a data mapper, said sequence controller, said address mapper, and said data mapper being respectively connected to said data bus interface for respectively receiving control, address and data signals as provided from the output thereof, a display controller connected to the output of said sequence controller, internal registers connected to the outputs of said address and data mappers, a graphics processor/local address-data bus interface connected to the output of said display controller and having an input adapted to be connected to a local address-data bus, an access arbitration controller connected to the outputs of said address mapper and said data mapper, said access arbitration controller also being connected to an output of said graphics processor/local address-data bus interface and having first and second outputs, and a memory controller connected to the output of said graphics processor/local address-data bus interface and the first and second outputs of said access arbitration controller; and means operably associated with said first and second memory parts for deriving graphics data to provide displays from the first and/or the second memory parts of said video memory for transmission to said display unit.

Claim 16

A video graphics display system set forth in claim 11, wherein said logic based hardware sub-system comprises a video graphics array hardware sub-system.