Simple temporary information storage circuit controllable with enable/reset signal

Claim 2

An addressing system comprising a plurality of address predecoder circuits for producing address predecoded signals from address bits indicative of a plurality of addresses in a time division multiplexing sequence, a first address decoder unit coupled to said plurality of address predecoders for producing first address decoded signals, a plurality of first temporary information storage circuits responsive to a first and a second control signals in a first phase for temporarily storing said first address decoded signals, a second address decoder unit coupled to said plurality of address predecoders for producing second address decoded signals, and a plurality of second temporary information storage circuits responsive to said first and second control signals in a second phase after said first phase for temporarily storing said second address decoded signals.

Claim 3

The temporary information storage circuit as set forth in claim 1, in which said addressing system further comprising a plurality of delayed latch circuits respectively associated with said plurality of address predecoder circuits for temporarily storing said address bits indicative of an address firstly supplied in the time division multiplexing sequence.

Claim 4

The addressing system of claim 1, wherein each of said plurality of first temporary information storage circuits and each of said plurality of second temporary information storage circuits comprises: a) a transfer transistor responsive to a first control signal so as to provide a signal path for an input signal indicative of a piece of information; b) a bistable circuit having an input node coupled to said transfer transistor, and responsive to said input signal for changing an output signal thereof; and c) a switching transistor coupled between a source of constant voltage and said input node of said bistable circuit, and responsive to a second control signal so that said bistable circuit forcibly changes said output signal to a certain level corresponding to said piece of information in an enabled state and to a reset level regardless of said piece of information in a reset state.

Claim 5

The addressing system as set forth in claim 3, wherein said bistable circuit is a flip flop circuit implemented by two inverters having respective input nodes and respective output nodes, one of said input nodes and one of said output nodes being coupled to said input node of said bistable circuit, the other of said input node being coupled to the other of said output node where said output signal is produced, one of said two inverters being smaller in current driving capability than a source of said input signal and said transfer transistor so that said input signal can change the voltage level at said input node of said bistable circuit.

Claim 6

The addressing system as set forth in claim 4, wherein said switching transistor is a p-channel enhancement type switching transistor gated by said second control signal, said second control signal designating said enable state by a high voltage level, to thereby keep said switching transistor in an off state.