System and method for formulating subsets of a hierarchical circuit design

Claim 2

A computer-implemented method for building in computer memory a subset of hierarehical circuit design data representing a physical design of a very large scale integrated (VLSI) circuit comprising the steps of: storing in the computer memory a VLSI design component identifying a leaf design entity in the hierarehical circuit design data; storing in the computer memory a set of placements in the hierarehical circuit design where the VLSI design component appears, the set of placements forming a subset of instances of the leaf design entity; associating with the VLSI design component and the placements a set of links, the links connecting various ones of the placements to one another to further denote placement of the VLSI design component within the hierarehical circuit design data; storing the set of links in the computer memory; storing in the computer memory a subset list in the form of a pruned graph appended to the VLSI design component, the subset list denoting the subset and including placements where the VLSI design component is identified in the hierarehical circuit design data, the pruned graph including leaf nodes and internal nodes, the leaf nodes and the internal nodes having associated instance counts, each instance count including first and second numbers, the second number being indicative of a total quantity of instances of a leaf design entity that could be represented at a node associated with the instance count; computing an instance count denoting a number of instances of the VLSI design component represented in the subset list; and appending the instance count to the subset list in the computer memory.

Claim 3

The method as recited in claim 1, further comprising the steps of: determining when new data is created, applicable only to some instances of a nested cell, whether the resulting subset will disturb the nesting structure of the represented circuit design; and associating with the subset list a subset attribute of instances of the leaf design entity conditionally excluded from the hierarehical circuit design data to avoid flattening the data.

Claim 4

The method as recited in claim 2, wherein the exclusion condition is defined by a user-written VLSI shape manipulation program.

Claim 5

The method as recited in claim 2, wherein the exclusion condition is enforced by a VLSI design verification system.

Claim 6

The method as recited in claim 2, further comprising the step of computing the complement of the subset list to generate a second subset list which identifies instances of the leaf design entity conditionally included in the hierarehical circuit design.

Claim 7

The method as recited in claim 2, further comprising the step of appending to the subset list a second subset list of exclusions to restore the excluded instances of the leaf design entity.

Claim 8

The method as recited in claim 1, further comprising the steps of: determining when new data is created, applicable only to some instances of a nested cell, whether the resulting subset will disturb the nesting structure of the represented circuit design; and associating with the subset list a subset attribute of instances of the leaf design entity conditionally included in the hierarehical circuit design.

Claim 9

The method as recited in claim 7, wherein the inclusion condition is defined by a user-written VLSI shape manipulation program.

Claim 10

The method as recited in claim 1, wherein for each internal node the first number in the instance count is set equal to the sum of the second numbers from the instance counts of the instances of the leaf design entity included in the subgraph of that internal node.

Claim 11

The method as recited in claim 1, wherein the highest node of the hierarehical tree structure is the root of the design tree and the placement of the VLSI design component within the hierarehical circuit design data includes placement in a higher level component in the hierarehical circuit design.

Claim 12

In a computer-based system for building a subset of hierarehical circuit design data of a physical design of a very large scale integrated (VLSI) circuit, comprising: computer memory means for storing a VLSI design component identifying a leaf design entity in the hierarehical circuit design and a set of placements in the hierarehical circuit design data where the VLSI design component appears, the set of placements forming a subset of instances of the leaf design entity; and processor means for associating with the VLSI design component and the placements stored in said memory means a set of links, the links connecting various ones of the placements to one another to further denote placement of the VLSI design component within the hierarehical circuit design, said processor means storing the set of links in said computer memory means and a subset list in the form of a pruned graph appended to the VLSI design component, the subset list denoting the subset and including placements where the VLSI design component is identified in the hierarehical circuit design data, the pruned graph including leaf nodes and internal nodes, the leaf nodes and the internal nodes having associated instance counts, each instance count including first and second numbers, the second number being indicative of a total quantity of instances of a leaf design entity that could be represented at a node associated with the instance count; said processor means computing an instance count denoting the number of instances of the VLSI design component represented in the subset list and appending the instance count to the subset list in said computer memory means.

Claim 13

In a computer-based system for building a subset of hierarehical circuit design data of a physical design of a very large scale integrated (VLSI) circuit, comprising: computer memory means for storing a VLSI design component identifying a leaf design entity in the hierarehical circuit design and a set of placements in the hierarehical circuit design data where the VLSI design component appears, the set of placements forming a subset of instances of the leaf design entity; and processor means for associating with the VLSI design component and the placements stored in said memory means a set of links, the links connecting various ones of the placements to one another to further denote placement of the VLSI design component within the hierarehical circuit design, said processor means storing the set of links in said computer memory means and a subset list in the form of a pruned graph appended to the VLSI design component, the subset list denoting the subset and including placements where the VLSI design component is identified in the hierarehical circuit design data, the pruned graph including leaf nodes and internal nodes, the leaf nodes and the internal nodes having associated instance counts, each instance count including first and second numbers, the second number being indicative of a total quantity of instances of a leaf design entity that could be represented at a node associated with the instance count; said processor means computing an instance count denoting the number of instances of the VLSI design component represented in the subset list and appending the instance count to the subset list in said computer memory means.

Claim 14

The system as recited in claim 11, wherein the subset list identifies instances of the leaf design entity conditionally excluded from the hierarehical circuit design, said processor means computing a complement of the subset list to generate a second subset list which identifies instances of the leaf design entity conditionally included in the hierarehical circuit design data.

Claim 15

The system as recited in claim 11, wherein the subset list identifies instances of the leaf design entity conditionally excluded from the hierarehical circuit design, said processor means appending to the subset list a second subset list of exclusions to restore the excluded instances of the leaf design entity.

Claim 16

The system as recited in claim 11, wherein for each leaf node, said processor means sets the first number in the instance count equal to the second number in the instance count.

Claim 17

The system as recited in claim 11, wherein for each internal node, said processor means sets the first number in the instance count equal to a sum of the second numbers from the instance counts of the instances of the leaf design entity included in a subgraph of that internal node.

Claim 18

The method recited in claim 1, further comprising the steps of: receiving a request to add an instance of a leaf design entity to the subset list; searching the subset list to determine whether the instance is already in the list; if the instance is not in the subset list, determining whether the instance represents an internal node of the pruned graph; if the instance represents an internal node, (a) converting the internal node by deleting a subtree of the internal node, (b) incrementing the first instance count of the leaf node to equal the second instance count of the leaf node, (c) incrementing the first instance count of each ancestor node to the leaf node by an increment amount applied to the first instance count of the leaf node; if the instance represents a non-internal node, (a) identifying an ancestor node common to the instance and the pruned graph, (b) appending the subgraph of the common ancestor of the instance to the common ancestor of the pruned graph, (c) identifying the leaf node of the appended subgraph, (d) initializing the first instance count of each node in the appended subgraph to zero and the second instance count to the total quantity of instances of the leaf design entity that could be represented at the node associated with the instance count, as determined from the hierarehical circuit design data, (e) setting the first instance count of the leaf node equal to the second instance count of the leaf node, (f) adding the second instance count of the leaf node to the first instance count of each ancestor node to the leaf node in the appended subgraph; and traversing the ancestor path from the leaf of the appended subgraph to determine for each node whether the first instance count equals the second instance count and (a) if the first instance count equals the second instance count, deleting the subgraph of that node, (b) if the first instance count does not equal the second instance count, terminating the traversal.

Claim 19

A computer-implemented method for adding to a subset of hierarehical circuit design data representing a physical design of a very large scale integrated (VLSI) circuit stored in computer memory, a subset list in the form of a pruned graph including leaf nodes and internal nodes being appended to a VLSI component in the hierarehical circuit design data and including placements where the VLSI component is identified in the hierarehical design data, the leaf nodes and the internal nodes having associated instance counts, each instance count including first and second numbers, the second number being indicative of a total quantity of instances of a leaf design entity that could be represented at a node with the instance count, said method comprising the steps of: receiving a request to add an instance of a leaf design entity to the subset list; searching the subset list to determine whether the instance is already in the list; if the instance is not in the subset list, determining whether the instance represents an internal node of the pruned graph; if the instance represents an internal node, (a) converting the internal node to a leaf node by deleting a subtree of the internal node, (b) incrementing the first instance count of the leaf node to equal the second instance count of the leaf node; (c) incrementing the first instance count of each ancestor node to the leaf node by the increment amount applied to the first instance count of the leaf node; if the instance represents a non-internal node, (a) identifying an ancestor node common to the instance and the pruned graph, (b) appending the subgraph of the common ancestor of the instance to the common ancestor of the pruned graph, (c) identifying the leaf node of the appended subgraph, (d) initializing the first instance count of each node in the appended subgraph to zero and the second instance count to the total quantity of instances of the leaf design entity that could be represented at the node associated with the instance count, as determined from the hierarehical circuit design, (e) setting the first instance count of the leaf node equal to the second instance count of the leaf node, (f) adding the second instance count of the leaf node to the first count of each ancestor node to the leaf node in the appended subgraph; and traversing the ancestor path from the leaf of the appended subgraph to determine for each node whether the first instance count equals the second instance count and (a) if the first instance count equals the second instance count, deleting the subgraph of that node, (b) if the first instance count does not equal the second instance count, terminating the traversal.

Claim 20

A computer-implemented method for adding to a subset of hierarehical circuit design data representing a physical design of a very large scale integrated (VLSI) circuit stored in computer memory, a subset list in the form of a pruned graph including leaf nodes and internal nodes being appended to a VLSI component in the hierarehical circuit design data and including placements where the VLSI component is identified in the hierarehical design data, the leaf nodes and the internal nodes having associated instance counts, each instance count including first and second numbers, the second number being indicative of a total quantity of instances of a leaf design entity that could be represented at a node with the instance count, said method comprising the steps of: receiving a request to add an instance of a leaf design entity to the subset list; searching the subset list to determine whether the instance is already in the list; if the instance is not in the subset list, determining whether the instance represents an internal node of the pruned graph; if the instance represents an internal node, (a) converting the internal node to a leaf node by deleting a subtree of the internal node, (b) incrementing the first instance count of the leaf node to equal the second instance count of the leaf node; (c) incrementing the first instance count of each ancestor node to the leaf node by the increment amount applied to the first instance count of the leaf node; if the instance represents a non-internal node, (a) identifying an ancestor node common to the instance and the pruned graph, (b) appending the subgraph of the common ancestor of the instance to the common ancestor of the pruned graph, (c) identifying the leaf node of the appended subgraph, (d) initializing the first instance count of each node in the appended subgraph to zero and the second instance count to the total quantity of instances of the leaf design entity that could be represented at the node associated with the instance count, as determined from the hierarehical circuit design, (e) setting the first instance count of the leaf node equal to the second instance count of the leaf node, (f) adding the second instance count of the leaf node to the first count of each ancestor node to the leaf node in the appended subgraph; and traversing the ancestor path from the leaf of the appended subgraph to determine for each node whether the first instance count equals the second instance count and (a) if the first instance count equals the second instance count, deleting the subgraph of that node, (b) if the first instance count does not equal the second instance count, terminating the traversal.