Patent US5526316A successfully refreshed from Google Patents.
US5526316A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial access memory device
Assignee: WINBOND ELETRONICS CORP
•
Filing: 1994-04-29
•
Granted: 1996-06-11
•
Expires: 2014-04-29
Abstract
Abstract The serial access memory device provided has a first data terminal and a memory cell array having a plurality of address locations. The serial access memory device comprises a shift register and an address decode circuit. The shift register, responsive to an address clock signal, stores a first address value of a serial access memory operation. The shift register has an input terminal coupled to the first data terminal. The address decode circuit serially accesses the plurality of address locations of the memory cell array, responsive to an access control signal, the first address value, the address clock signal and the clock signal.
Inventors
- 👤 James J. Y. Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:00
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
247 words
A serial access memory device comprising: a single data terminal for serially receiving an address signal during a first period of time and for serially transmitting or receiving a plurality of sets of data signal during a second different period of time; a memory cell array having a plurality of address locations each of which stores one of the plurality of sets of data signal; a shift register, in response to an address clock signal, for storing a first address value of a serial access memory operation, the first address value received from the single data terminal during the first period of time; an address decode circuit for serially accessing the plurality of address locations of said memory cell array, in response to a read access or a write access control signal, the first address value, the address clock signal, and a clock signal; wherein, during the second different period of time and with the write access control signal being asserted, the plurality of sets of data signal, which are serially received through the single data terminal, are stored at the plurality of address locations in response to the write access control signal and the clock signal, and during the second different period of time and with the read access control signal being asserted, the plurality of sets of data signal from the plurality of address locations are transmitted serially through the single data terminal in response to the read access control signal and the clock signal.
Claim 2
Dependent Claim
247 words
A serial access memory device comprising: a single data terminal for serially receiving an address signal during a first period of time and for serially transmitting or receiving a plurality of sets of data signal during a second different period of time; a memory cell array having a plurality of address locations each of which stores one of the plurality of sets of data signal; a shift register, in response to an address clock signal, for storing a first address value of a serial access memory operation, the first address value received from the single data terminal during the first period of time; an address decode circuit for serially accessing the plurality of address locations of said memory cell array, in response to a read access or a write access control signal, the first address value, the address clock signal, and a clock signal; wherein, during the second different period of time and with the write access control signal being asserted, the plurality of sets of data signal, which are serially received through the single data terminal, are stored at the plurality of address locations in response to the write access control signal and the clock signal, and during the second different period of time and with the read access control signal being asserted, the plurality of sets of data signal from the plurality of address locations are transmitted serially through the single data terminal in response to the read access control signal and the clock signal.
Claim 3
Dependent Claim
84 words
The memory device as recited in claim 1, wherein the shift register includes N data registers coupled together in series to form said shift register, each of the N data registers having a data output terminal (Q), a clock input terminal (CLK) and a data input terminal (D), the data input terminal of a first data register of the N data registers coupled to the single data terminal, the clock input terminal of each data register being adapted to receive the address clock signal.
Claim 4
Dependent Claim
65 words
The memory device as recited in claim 2, wherein the address decode circuit includes an address latch/counter which has N input terminals each of which is coupled to the data output terminal (Q) of one corresponding data register, for latching the first address value in response to a load signal, and for incrementing the value of the address latch/counter in response to an increment signal.
Claim 5
Dependent Claim
36 words
The memory device as recited in claim 1, wherein the address decode circuit includes an EOM terminal for sending an End of Memory signal when a last address location of the memory cell array is accessed.
Claim 6
Dependent Claim
45 words
The memory device as recited in claim 3, wherein the address decode circuit further comprising: an edge detector, in response to the read or write access control signals, the address clock signal and the clock signal, to generate the load signal and the increment signal.
Claim 7
Dependent Claim
169 words
The memory device as recited in claim 5, wherein the edge detector comprising: a NAND gate having two inputs receiving the read access control signal and the write access control signal respectively, and having an output generating the increment signal; a first NOR gate having a first input, a second input and a first output, the first input receiving the increment signal; a second NOR gate having a third input, a fourth input and a second output, the third input receiving the address clock signal, the fourth input being coupled to the first output of the first NOR gate, and the second output being coupled to the second input of the first NOR gate and generating a second output signal; an inverter having a fifth input and a third output, the fifth input being coupled to the second output of the second NOR gate, the third output generating a third output signal; an AND gate, in response to the second and third output signal, for generating the load signal.
Claim 8
Dependent Claim
170 words
A serial access memory device, comprising: a single data terminal for serially receiving an address signal during a first period of time, and for serially transmitting or receiving a plurality of sets of data signal during a second different period of time; a memory cell array having a plurality of address locations; a data buffer, coupled to the single data terminal and the memory cell array respectively, wherein, during the second different period of time and with a write access control signal being asserted, the plurality of sets of data signal, which are serially received through the single data terminal, are stored at the plurality of address locations in response to the write access control signal and a clock signal, and during the second different period of time and with a read access control signal being asserted, the plurality of sets of data signal from the plurality of address locations are transmitted serially through the single data terminal in response to the read access control signal and the clock signal.
Claim 9
Dependent Claim
170 words
A serial access memory device, comprising: a single data terminal for serially receiving an address signal during a first period of time, and for serially transmitting or receiving a plurality of sets of data signal during a second different period of time; a memory cell array having a plurality of address locations; a data buffer, coupled to the single data terminal and the memory cell array respectively, wherein, during the second different period of time and with a write access control signal being asserted, the plurality of sets of data signal, which are serially received through the single data terminal, are stored at the plurality of address locations in response to the write access control signal and a clock signal, and during the second different period of time and with a read access control signal being asserted, the plurality of sets of data signal from the plurality of address locations are transmitted serially through the single data terminal in response to the read access control signal and the clock signal.
Claim 10
Dependent Claim
48 words
The memory device as recited in claim 7, further comprising: a shift register, in response to an address clock signal, for storing a first address value of a serial access memory operation, the first address value received from the single data terminal during the first period of time.
Claim 11
Dependent Claim
84 words
The memory device as recited in claim 8, wherein the shift register includes N data registers coupled together in series to form said shift register, each of the N data registers having a data output terminal (Q), a clock input terminal (CLK) and a data input terminal (D), the data input terminal of a first data register of the N data registers coupled to the single data terminal, the clock input terminal of each data register being adapted to receive the address clock signal.
Claim 12
Dependent Claim
65 words
The memory circuit as recited in claim 9, wherein the address decode circuit includes an address latch/counter which has N input terminals each of which is coupled to the data output terminal (Q) of one corresponding data register, for latching the first address value in response to a load signal and for incrementing the value of the address latch/counter in response to an increment signal.
Claim 13
Dependent Claim
36 words
The memory device as recited in claim 7, wherein the address decode circuit includes an EOM terminal for sending an End of Memory signal when a last address location of the memory cell array is accessed.
Claim 14
Dependent Claim
46 words
The memory device as recited in claim 10, wherein the address decode circuit further comprising: an edge detector, in response to the read access or write access control signals, the address clock signal and the clock signal, to generate the load signal and the increment signal.
Claim 15
Dependent Claim
169 words
The memory device as recited in claim 12, wherein the edge detector comprising: a NAND gate having two inputs receiving the read access control signal and the write access control signal respectively, and having an output generating the increment signal; a first NOR gate having a first input, a second input and a first output, the first output receiving the increment signal; a second NOR gate having a third input, a fourth input and a second output, the third input receiving the address clock signal, the fourth input being coupled to the first output of the first NOR gate, and the second output being coupled to the second input of the first NOR gate and generating a second output signal; an invertor having a fifth input and a third output, the fifth input being coupled to the second output of the second NOR gate, the third output generating a third output signal; an AND gate, in response to the second and third output signal, for generating the load signal.
Claim 16
Dependent Claim
42 words
The memory device as recited in claim 1 further comprising: a reset circuit, in response to the read access or write access control signal, the clock signal and the address clock signal, for generating a reset signal to reset the shift register.
Claim 17
Dependent Claim
85 words
The memory device as recited in claim 14, wherein the shift register includes N data registers coupled together in series to form said shift register, each of the N data registers having a data output terminal (Q), a clock input terminal (CLK) and a data input terminal (D), the data input terminal of a first data register of the N data registers coupled to the single data input terminal, the clock input terminal of each data register being adapted to receive the address clock signal.
Claim 18
Dependent Claim
64 words
The memory device as recited in claim 15, wherein the address decode circuit includes an address latch/counter which has N input terminals each of which being coupled to the data output terminal of one corresponding data register, for latching the first address value in response to a load signal and for incrementing the value of the address latch/counter in response to an increment signal.
Claim 19
Dependent Claim
36 words
The memory device as recited in claim 14, wherein the address decode circuit includes an output terminal for sending an End of Memory signal when a last address location of the memory cell array is accessed.
Claim 20
Dependent Claim
46 words
The memory device as recited in claim 16, wherein the address decode circuit further comprising: an edge detector, in response to the read access or write access control signals, the address clock signal and the clock signal, to generate the load signal and the increment signal.
Claim 21
Dependent Claim
168 words
The memory device as recited in claim 18, wherein the edge detector comprising: a NAND gate having two inputs receiving the read access control signal and the write access control signal respectively, and having output generating the increment signal; a first NOR gate having a first input, a second input and a first output, the first input receiving the increment signal; a second NOR gate having a third input, a fourth input and a second output, the third input receiving the address clock signal, the fourth input being coupled to the first output of the first NOR gate, and the second output being coupled to the second input of the first NOR gate and generating a second output signal; an inverter having a fifth input and a third output, the fifth input being coupled to the second output of the second NOR gate, the third output generating a third output signal; an AND gate, in response to the second and third output signal, for generating the load signal.
Claim 22
Dependent Claim
169 words
The memory device as recited in claim 14, wherein the reset circuit comprising: a NAND gate having two inputs receiving the read access control signal and the write access control signal respectively, and having an output; a first NOR gate having a first input, a second input and a first output, the first input coupled to the output of the NAND gate; a second NOR gate having a third input, a fourth input and a second output, the third input receiving the address clock signal, the fourth input being coupled to the first output of the first NOR gate, and the second output being coupled to the second input of the first NOR gate and generating a second output signal; an inverter having a fifth input and a third output, the fifth input being coupled to the second output of the second NOR gate, the third output generating a third output signal; a NOR gate, in response to the second and third output signal, for generating the reset signal.
References Cited (Backward Citations)
US4159541A
Cited
US4677594A
Cited
US4802134A
Cited
US4870621A
Cited
US4903242A
Cited
US4873671A
Cited
US5198999A
Cited
US5265049A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-11 | 1999-12-11 | 2000-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-11 | 2003-12-11 | 2004-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-11 | 2007-12-11 | 2008-06-11 | $7700.00 | Window Closed / Lapsed |