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US5544104A
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Virtual crosspoint memory
Assignee: Texas Instruments Inc
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Filing: 1995-03-14
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Granted: 1996-08-06
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Expires: 2015-03-14
Abstract
Abstract An interconnection-point memory which includes an array of N1 input buses (Rj) intended to be connected to a first plurality of N1 data-sender devices, an array of N2 output buses (Ck) intended to be connected to a second plurality of N2 data-receiver devices, and interconnection means (17) for connecting the array of input buses to the array of output buses. The interconnection means include on the one hand, a third plurality of N3 switching memories (FIFO m) used as first-in, first-out FIFO devices provided with a write port (Din) and with a read port (Dout), and on the other hand, first control means (S[j,m],24a,24b) for connecting in a virtual manner the input port of at least one switching memory to a specified input bus, and second control means (S[k,m],24a',24b') for connecting in a virtual manner at least one output bus to the read port of the said switching memory, so that the said specified switching memory constitutes a temporary interconnection point, independent of the input buses and output buses to be interconnected. This interconnection-point memory enables Application to the asynchronous transfer of data between senders and receivers.
Inventors
- 👤 Gerard Chauvel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:34
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/106; H04L49/108; H04L49/15; H04L49/1553; H04L49/1576; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L2012/5678; H04L2012/5681
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
217 words
An interconnection-point memory comprising: an array of a first plurality of input buses for connection to a first plurality of data-sender devices having the same number as the number of input buses included in the first plurality of input buses; an array of a second plurality of output buses for connection to a second plurality of data-receiver devices having the same number as the number of output buses included in the second plurality of output buses; a third plurality of switching memories, each of said third plurality of switching memories defining a first-in, first-out FIFO memory device having a write port and a read port; first control means operably interposed between said third plurality of switching memories and said first plurality of input buses for temporarily connecting in a virtual manner the write port of at least one selected switching memory to a selected input bus; and second control means operably interposed between said second plurality of output buses and said third plurality of switching memories for temporarily connecting in a virtual manner at least one output bus to the read port of said one selected switching memory, said one selected switching memory thereby constituting a temporary interconnection point independent of the first plurality of input buses and the second plurality of output buses to be interconnected.
Claim 2
Dependent Claim
217 words
An interconnection-point memory comprising: an array of a first plurality of input buses for connection to a first plurality of data-sender devices having the same number as the number of input buses included in the first plurality of input buses; an array of a second plurality of output buses for connection to a second plurality of data-receiver devices having the same number as the number of output buses included in the second plurality of output buses; a third plurality of switching memories, each of said third plurality of switching memories defining a first-in, first-out FIFO memory device having a write port and a read port; first control means operably interposed between said third plurality of switching memories and said first plurality of input buses for temporarily connecting in a virtual manner the write port of at least one selected switching memory to a selected input bus; and second control means operably interposed between said second plurality of output buses and said third plurality of switching memories for temporarily connecting in a virtual manner at least one output bus to the read port of said one selected switching memory, said one selected switching memory thereby constituting a temporary interconnection point independent of the first plurality of input buses and the second plurality of output buses to be interconnected.
Claim 3
Dependent Claim
115 words
An interconnection-point memory as set forth in claim 1, wherein said first control means comprises a first plurality of input multiplexor circuits for each of said third plurality of switching memories, said first plurality of input multiplexor circuits being operable to multiplex the first plurality of input buses to the write port of a selected switching memory of said third plurality of switching memories; said first control means further including a first control register for each of said input multiplexor circuits included in said first plurality of input multiplexor circuits and operably connected thereto for enabling or disabling the said input multiplexor circuit corresponding thereto dependent upon the binary content of said first control register.
Claim 4
Dependent Claim
117 words
An interconnection-point memory as set forth in claim 2, wherein said second control means comprises a second plurality of output multiplexor circuits for each of said third plurality of switching memories, said second plurality of output multiplexor circuits being operable to multiplex the read port of the said selected switching memory of said third plurality of switching memories to the second plurality of output buses; and said second control means further including a second control register for each of said output multiplexor circuits included in said second plurality of output multiplexor circuits and operably connected thereto for enabling or disabling the said output multiplexor circuit corresponding thereto dependent upon the binary content of said second control register.
Claim 5
Dependent Claim
100 words
An interconnection-point memory as set forth in claim 3, wherein said first plurality of input buses and said second plurality of output buses include data and address bits transmitted by the first plurality of data-sender devices to the corresponding input multiplexor circuits and by the corresponding output multiplexor circuits to the second plurality of data-receiver devices; control bits transmitted to said first control registers associated with each input multiplexor circuit and said second control registers associated with each output multiplexor circuit in ensuring interconnection between a selected data and input address bus and a selected data and output address bus.
Claim 6
Dependent Claim
43 words
An interconnection-point memory as set forth in claim 3, wherein each of said first and second control registers operably associated with said first plurality of input multiplexor circuits and said second plurality of output multiplexor circuits comprises flip-flops mounted in a shift-register mode.
Claim 7
Dependent Claim
43 words
An interconnection-point circuit as set forth in claim 3, further including a read amplification circuit connected between the read port of each of said third plurality of switching memories and the corresponding output multiplexor circuits of the second plurality of output multiplexor circuits.
Claim 8
Dependent Claim
46 words
An interconnection-point memory as set forth in claim 1, wherein each of said second plurality of output buses has an output buffer circuit; and a plurality of read amplification circuits arranged together to define a group of read amplification circuits connected to said output buffer circuit.
Claim 9
Dependent Claim
60 words
An interconnection-point memory as set forth in claim 1, wherein the number of switching memories included in said third plurality of switching memories is smaller than the number of interconnection points for the interconnection-point memory as defined by multiplying the number represented by the first plurality of input buses by the number represented by the second plurality of output buses.
References Cited (Backward Citations)
US5109361A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |