System and method for processing an instruction in a processing system

Claim 3

The method of claim 1 wherein said second instruction is an execution serialized instruction preceded in a sequence by said first instruction.

Claim 4

The method of claim 1 wherein said step of outputting said signal comprises the step of outputting said signal in response determining said first instruction is for execution by said execution circuitry in an imprecise nonrecoverable exception mode.

Claim 5

The method of claim 2 wherein said step of initiating execution comprises the step of initiating execution of said execution serialized instruction with said execution circuitry in response to said signal, prior to said execution circuitry finishing executing said first instruction.

Claim 6

The method of claim 4 wherein said execution serialized instruction is preceded in said sequence by a different instruction, and said execution serialized instruction has an information dependency upon a result of said different instruction.

Claim 7

The method of claim 5 wherein said step of initiating execution comprises the step of initiating execution of said execution serialized instruction in response to said signal, only if said execution circuitry has finished executing said different instruction.

Claim 8

The method of claim 4 and further comprising the step of executing a first stage of said execution serialized instruction with said execution circuitry, prior to initiating execution of a second stage of said execution serialized instruction with said execution circuitry in response to said signal.

Claim 9

The method of claim 7 wherein said executing step comprises the step of executing said first stage, prior to initiating execution of said second stage in response to said signal, prior to said execution circuitry finishing executing said first instruction.

Claim 10

The method of claim 8 wherein said execution serialized instruction is a Store instruction.

Claim 11

The method of claim 1 and further comprising the step of storing an indication in a reorder buffer in response to said signal.

Claim 12

The method of claim 10 wherein said storing step comprises the step of storing said indication in said reorder buffer only if said first instruction is of a type to be executed speculatively.

Claim 13

The method of claim 10 and further comprising the step of deleting said indication in said reorder buffer in response to said initiating execution of said second instruction.

Claim 14

The method of claim 1 wherein said step of initiating execution comprises the step of initiating execution of said second instruction, only if at least one of the following conditions (a) and (b) is true for each preceding instruction which precedes said second instruction in a sequence of instructions dispatched to said execution circuitry for execution: (a) an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (b) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 15

A processing system, comprising: execution circuitry for executing first and second instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said first and second instructions to said execution circuitry for execution; and outputting a signal in response to determining an exception is an impossible consequence of said execution circuitry executing said first instruction; and said execution circuitry being operable to initiate execution of said second instruction in response to said signal, independent of whether said execution circuitry has finished executing said first instruction.

Claim 16

A processing system, comprising: execution circuitry for executing first and second instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said first and second instructions to said execution circuitry for execution; and outputting a signal in response to determining an exception is an impossible consequence of said execution circuitry executing said first instruction; and said execution circuitry being operable to initiate execution of said second instruction in response to said signal, independent of whether said execution circuitry has finished executing said first instruction.

Claim 17

The system of claim 14 wherein said second instruction is an execution serialized instruction preceded in a sequence by said first instruction.

Claim 18

The system of claim 15 wherein said execution circuitry comprises: a first execution unit for executing said first instruction; and a second execution unit for executing said execution serialized instruction.

Claim 19

The system of claim 15 wherein said execution circuitry initiates execution of said execution serialized instruction in response to said signal, prior to said execution circuitry finishing executing said first instruction.

Claim 20

The system of claim 17 wherein said execution serialized instruction is preceded in said sequence by a different instruction, and said execution serialized instruction has an information dependency upon a result of said different instruction.

Claim 21

The system of claim 18 wherein said execution circuitry initiates execution of said execution serialized instruction in response to said signal, only if said execution circuitry has finished executing said different instruction.

Claim 22

The system of claim 17 wherein said execution circuitry executes a first stage of said execution serialized instruction, prior to said execution circuitry initiating execution of a second stage of said execution serialized instruction in response to said signal.

Claim 23

The system of claim 20 wherein said execution circuitry initiates execution of said second stage in response to said signal, prior to said execution circuitry finishing executing said first instruction.

Claim 24

The system of claim 21 wherein said execution serialized instruction is a Store instruction.

Claim 25

The system of claim 14 and further comprising: a reorder buffer; and control circuitry coupled to said dispatch circuitry and to said reorder buffer for storing an indication in said reorder buffer in response to said signal.

Claim 26

The system of claim 23 wherein said control circuitry stores said indication in said reorder buffer only if said first instruction is of a type to be executed speculatively.

Claim 27

The system of claim 23 wherein said control circuitry is operable to delete said indication in said reorder buffer in response to said execution circuitry initiating execution of said second instruction.

Claim 28

The system of claim 14 wherein said execution circuitry initiates execution of said second instruction, only if at least one of the following conditions (a) and (b) is true for each preceding instruction which precedes said second instruction in a sequence of instructions dispatched by said dispatch circuitry to said execution circuitry for execution: (a) an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (b) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 29

The system of claim 14 wherein said dispatch circuitry is further operable to output said signal in response to determining said first instruction is for execution by said execution circuitry in an imprecise nonrecoverable exception mode.

Claim 30

The system of claim 14 wherein said execution circuitry comprises: at least one execution unit; and execution serialization logic.

Claim 33

The method of claim 29 wherein said particular instruction is an execution serialized instruction.

Claim 36

The method of claim 31 and further comprising the step of storing an indication in a reorder buffer in response to said signal.

Claim 37

The method of claim 32 and further comprising the step of deleting said indication in said reorder buffer in response to said initiating execution of said second instruction.

Claim 38

The method of claim 31 wherein said step of initiating execution comprises the step of initiating execution of said second instruction, only if at least one of the following conditions (a), (b) and (c) is true for each preceding instruction which precedes said second instruction in a sequence of instructions dispatched to said execution circuitry for execution: (a) said preceding instruction is an instruction for execution by said execution circuitry in said imprecise nonrecoverable exception mode; (b) an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (c) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 39

The method of claim 31 wherein said second instruction is an execution serialized instruction preceded in a sequence by said first instruction.

Claim 40

The method of claim 35 wherein said step of initiating execution comprises the step of initiating execution of said execution serialized instruction with said execution circuitry in response to said signal, prior to said execution circuitry finishing executing said first instruction.

Claim 41

The method of claim 31 wherein said outputting step comprises the step of outputting said signal in response to determining said first instruction is a floating point instruction for execution by said execution circuitry in an imprecise nonrecoverable floating point exception mode.

Claim 42

A processing system, comprising: execution circuitry for executing first and second instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said first and second instructions to said execution circuitry for execution; and outputting a signal in response to determining said first instruction is for execution by said execution circuitry in an imprecise nonrecoverable exception mode; and said execution circuitry being operable to initiate execution of said second instruction response to said signal, independent of whether said execution circuitry has finished executing said first instruction.

Claim 43

A processing system, comprising: execution circuitry for executing first and second instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said first and second instructions to said execution circuitry for execution; and outputting a signal in response to determining said first instruction is for execution by said execution circuitry in an imprecise nonrecoverable exception mode; and said execution circuitry being operable to initiate execution of said second instruction response to said signal, independent of whether said execution circuitry has finished executing said first instruction.

Claim 44

The system of claim 38 and further comprising: a reorder buffer; and control circuitry coupled to said dispatch circuitry and to said reorder buffer for storing an indication in said reorder buffer in response to said signal.

Claim 45

The system of claim 34 wherein said control circuitry is operable to delete said indication in said reorder buffer in response to said execution circuitry initiating execution of said second instruction.

Claim 46

The system of claim 38 wherein said execution circuitry initiates execution of said second instruction, only if at least one of the following conditions (a), (b) and (c) is true for each preceding instruction which precedes said second instruction in a sequence of instructions dispatched by said dispatch circuitry to said execution circuitry for execution: (a) said dispatch circuitry determines said preceding instruction is an instruction for execution by said execution circuitry in said imprecise nonrecoverable exception mode; (b) said dispatch circuitry determines an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (c) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 47

The system of claim 38 wherein said wherein said second instruction is an execution serialized instruction preceded in a sequence by said first instruction.

Claim 48

The system of claim 42 wherein said execution circuitry initiates execution of said execution serialized instruction in response to said signal, prior to said execution circuitry finishing executing said first instruction.

Claim 49

The system of claim 38 wherein said dispatch circuitry outputs said signal in response to determining said first instruction is a floating point instruction for execution by said execution circuitry in an imprecise nonrecoverable floating point exception mode.

Claim 50

The system of claim 38 wherein said execution circuitry comprises: a first execution unit for executing said first instruction; and a second execution unit for executing said second instruction.

Claim 51

A processing system, comprising: execution circuitry for executing a sequence of instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said sequence of instructions to said execution circuitry for execution; and for each said instruction, prior to said execution circuitry finishing execution of said instruction, outputting a first signal if said instruction is for execution by said execution circuitry in an imprecise nonrecoverable exception mode, and outputting a second signal in response to determining an exception is an impossible consequence of said execution circuitry executing said instruction; and said execution circuitry being operable to: for each said instruction, after said execution circuitry finishing execution of said instruction, output a third signal if an exception does not actually result from said execution circuitry executing said instruction; and initiate execution of a particular instruction in response to said first, second and third signals, independent of whether said execution circuitry has finished executing each preceding instruction which precedes said particular instruction in said sequence, only if at least one of the following conditions (a), (b) and (c) is true for each said preceding instruction: (a) said preceding instruction is for execution by said execution circuitry in said imprecise nonrecoverable exception mode; (b) an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (c) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 52

A processing system, comprising: execution circuitry for executing a sequence of instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said sequence of instructions to said execution circuitry for execution; and for each said instruction, prior to said execution circuitry finishing execution of said instruction, outputting a first signal if said instruction is for execution by said execution circuitry in an imprecise nonrecoverable exception mode, and outputting a second signal in response to determining an exception is an impossible consequence of said execution circuitry executing said instruction; and said execution circuitry being operable to: for each said instruction, after said execution circuitry finishing execution of said instruction, output a third signal if an exception does not actually result from said execution circuitry executing said instruction; and initiate execution of a particular instruction in response to said first, second and third signals, independent of whether said execution circuitry has finished executing each preceding instruction which precedes said particular instruction in said sequence, only if at least one of the following conditions (a), (b) and (c) is true for each said preceding instruction: (a) said preceding instruction is for execution by said execution circuitry in said imprecise nonrecoverable exception mode; (b) an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (c) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 53

The system of claim 44 wherein said particular instruction is an execution serialized instruction.

Claim 54

The system of claim 47 wherein said dispatch circuitry outputs said first signal if said instruction is a floating point instruction for execution by said execution circuitry in an imprecise nonrecoverable floating point exception mode.

Claim 55

The system of claim 44 wherein said execution circuitry comprises: a first execution unit for executing said particular instruction; and a second execution unit for executing at least one said preceding instruction.

Claim 56

A processing system, comprising: execution circuitry for executing a sequence of instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said sequence of instructions to said execution circuitry for execution; and for each said instruction, prior to said execution circuitry finishing execution of said instruction, outputting a first signal if an exception is an impossible consequence of said execution circuitry executing said instruction; and said execution circuitry being operable to: for each said instruction, after said execution circuitry finishing execution of said instruction, output a second signal if an exception does not actually result from said execution circuitry executing said instruction; and initiate execution of a particular instruction in response to said first and second signals, independent of whether said execution circuitry has finished executing each preceding instruction which precedes said particular instruction in said sequence, only if at least one of the following conditions (a) and (b) is true for each said preceding instruction: (a) an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (b) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 57

A processing system, comprising: execution circuitry for executing a sequence of instructions; dispatch circuitry coupled to said execution circuitry for: dispatching said sequence of instructions to said execution circuitry for execution; and for each said instruction, prior to said execution circuitry finishing execution of said instruction, outputting a first signal if an exception is an impossible consequence of said execution circuitry executing said instruction; and said execution circuitry being operable to: for each said instruction, after said execution circuitry finishing execution of said instruction, output a second signal if an exception does not actually result from said execution circuitry executing said instruction; and initiate execution of a particular instruction in response to said first and second signals, independent of whether said execution circuitry has finished executing each preceding instruction which precedes said particular instruction in said sequence, only if at least one of the following conditions (a) and (b) is true for each said preceding instruction: (a) an exception is an impossible consequence of said execution circuitry executing said preceding instruction; and (b) an exception does not actually result from said execution circuitry executing said preceding instruction.

Claim 58

The system of claim 50 wherein said particular instruction is an execution serialized instruction.

Claim 59

The system of claim 50 wherein said execution circuitry comprises: a first execution unit for executing said particular instruction; and a second execution unit for executing at least one said preceding instruction.

Claim 62

The method of claim 53 wherein said particular instruction is an execution serialized instruction.

Claim 63

The method of claim 54 wherein said step of outputting said first signal comprises the step of outputting said first signal if said instruction is a floating point instruction for execution by said execution circuitry in an imprecise nonrecoverable floating point exception mode.