US5554552A
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PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-04-03
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Granted: 1996-09-10
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Expires: 2015-04-03
Abstract
Abstract Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl3 doping are required to fabricate this device. The threshold voltage of this device is well controlled by the ratio of Cfp, capacitance of the P type capacitor and Cfn capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.
Inventors
- 👤 Kao M. Chi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:02
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/40; H10B41/42; H10B41/49; H10B69/00; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; Y; Y10; Y10S; Y10S438/00; Y10S438/901
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
129 words
A method of forming a floating gate ROM device comprising providing a lightly doped P- semiconductor substrate, forming a doped source region and a doped drain region in the substrate, forming a tunnel oxide layer and field oxide regions formed over the surface of the substrate, forming a PN junction floating gate electrode from a first polysilicon layer comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region, forming an intergate electrode dielectric layer covering the PN floating gate electrode, forming a polysilicon control gate electrode from a second polysilicon layer over the intergate electrode dielectric layer, and forming an additional dielectric layer over the control gate electrode.
Claim 2
Independent Claim
129 words
A method of forming a floating gate ROM device comprising providing a lightly doped P- semiconductor substrate, forming a doped source region and a doped drain region in the substrate, forming a tunnel oxide layer and field oxide regions formed over the surface of the substrate, forming a PN junction floating gate electrode from a first polysilicon layer comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region, forming an intergate electrode dielectric layer covering the PN floating gate electrode, forming a polysilicon control gate electrode from a second polysilicon layer over the intergate electrode dielectric layer, and forming an additional dielectric layer over the control gate electrode.
Claim 3
Dependent Claim
81 words
A method in accordance with claim 1 wherein the PN junction is formed by the steps comprising depositing a first polysilicon layer on the tunnel oxide layer and the field oxide regions, performing a P-type capacitor implant into the first polysilicon layer, forming a mask over the field oxide regions with openings over the tunnel oxide regions, and performing a N-type capacitor implant into portions of the first polysilicon layer over the tunnel oxide regions through the openings in the mask.
Claim 4
Dependent Claim
150 words
A method in accordance with claim 1 wherein the PN junction is formed by the further steps comprising performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×10 14 /cm 2 to about 3×10 14 /cm 2 , and formation of a first polysilicon layer N-type capacitor implant mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×10 15 /cm 2 to about 3×10 15 /cm 2 .
Claim 5
Dependent Claim
50 words
A method in accordance with claim 3 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.
Claim 6
Dependent Claim
59 words
A method in accordance with claim 4 wherein the resulting concentration of P dopant in the first polysilicon layer is from about 6×10 18 ions/cm 3 to about 2×10 19 ions/cm 3 , and the resulting concentration of N dopant in the first polysilicon layer is from about 6×10 19 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 7
Dependent Claim
151 words
A method in accordance with claim 2 wherein the PN junction is formed by the further steps comprising performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×10 14 /cm 2 to about 3×10 14 /cm 2 , and formation of a first polysilicon layer N-type capacitor implant photoresist mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×10 15 /cm 2 to about 3×10 15 /cm 2 .
Claim 8
Dependent Claim
50 words
A method in accordance with claim 6 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.
Claim 9
Dependent Claim
59 words
A method in accordance with claim 7 wherein the resulting concentration of P dopant in the first polysilicon layer is from about 6×10 18 ions/cm 3 to about 2×10 19 ions/cm 3 , and the resulting concentration of N dopant in the first polysilicon layer is from about 6×10 19 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 10
Dependent Claim
99 words
A method in accordance with claim 6 wherein the PN junction implanting of N ions is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV, and the resulting concentration of P dopant in the first polysilicon layer is from about 6×10 18 ions/cm 3 to about 2×10 19 ions/cm 3 , and the resulting concentration of N dopant in the first polysilicon layer is from about 6×10 19 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 11
Dependent Claim
32 words
A method of forming a floating gate ROM device in accordance with claim 9 wherein the first polysilicon layer has a thickness from about 1.5 k Å to about 2 k Å.
Claim 12
Independent Claim
146 words
A method of forming a floating gate ROM device comprising forming a lightly doped P- semiconductor substrate, forming a doped source region and a doped drain region in the substrate, forming a tunnel oxide layer and field oxide regions over the surface of the substrate, a PN junction floating gate electrode comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region, forming an interpolysilicon ONO dielectric layer covering the PN floating gate electrode, forming a polysilicon control gate electrode over the ONO dielectric layer, forming an additional dielectric layer over the control gate electrode with a via opening down to the drain region, and forming an electrical conductor over the additional dielectric layer extending down into the via opening into contact with the drain region.
Claim 13
Independent Claim
146 words
A method of forming a floating gate ROM device comprising forming a lightly doped P- semiconductor substrate, forming a doped source region and a doped drain region in the substrate, forming a tunnel oxide layer and field oxide regions over the surface of the substrate, a PN junction floating gate electrode comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region, forming an interpolysilicon ONO dielectric layer covering the PN floating gate electrode, forming a polysilicon control gate electrode over the ONO dielectric layer, forming an additional dielectric layer over the control gate electrode with a via opening down to the drain region, and forming an electrical conductor over the additional dielectric layer extending down into the via opening into contact with the drain region.
Claim 14
Dependent Claim
81 words
A method in accordance with claim 11 wherein the PN junction is formed by the steps comprising depositing a first polysilicon layer on the tunnel oxide layer and the field oxide regions, performing a P-type capacitor implant into the first polysilicon layer, forming a mask over the field oxide regions with openings over the tunnel oxide regions, and performing a N-type capacitor implant into portions of the first polysilicon layer over the tunnel oxide regions through the openings in the mask.
Claim 15
Dependent Claim
152 words
A method in accordance with claim 11 wherein the PN junction is formed by the further steps comprising performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×10 14 /cm 2 to about 3×10 14 /cm 2 , and formation of a first polysilicon layer N-type capacitor implant photoresist mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form type N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×10 15 /cm 2 to about 3×10 15 /cm 2 .
Claim 16
Dependent Claim
50 words
A method in accordance with claim 13 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.
Claim 17
Dependent Claim
59 words
A method in accordance with claim 14 wherein the resulting concentration of P dopant in the first polysilicon layer is from about 6×10 18 ions/cm 3 to about 2×10 19 ions/cm 3 , and the resulting concentration of N dopant in the first polysilicon layer is from about 6×10 19 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 18
Dependent Claim
150 words
A method in accordance with claim 12 wherein the PN junction is formed by the further steps comprising performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×10 14 /cm 2 to about 3×10 14 /cm 2 and formation of a first polysilicon layer N-type capacitor implant photoresist mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×10 15 /cm 2 to about 3×10 15 /cm 2 .
Claim 19
Dependent Claim
50 words
A method in accordance with claim 16 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.
Claim 20
Dependent Claim
59 words
A method in accordance with claim 17 wherein the resulting concentration of P dopant in the first polysilicon layer is from about 6×10 18 ions/cm 3 to about 2×10 19 ions/cm 3 , and the resulting concentration of N dopant in the first polysilicon layer is from about 6×10 19 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 21
Dependent Claim
99 words
A method in accordance with claim 16 wherein the PN junction implanting of N ions is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV, and the resulting concentration of P dopant in the first polysilicon layer is from about 6×10 19 ions/cm 3 to about 2×10 19 ions/cm 3 , and the resulting concentration of N dopant in the first polysilicon layer is from about 6×10 19 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 22
Dependent Claim
32 words
A method of forming a floating gate ROM device in accordance with claim 19 wherein the first polysilicon layer has a thickness from about 1.5 k Å to about 2 k Å.
References Cited (Backward Citations)
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