System and method for dynamic bus access prioritization and arbitration based on changing bus master request frequency

Claim 2

In a computer system having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, an arbitration circuit for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising: a tabulation circuit for tabulating a relative request activity of each of said plurality of devices; and a comparison circuit coupled to said tabulation circuit for granting only one of said coinciding requests as a function of said relative request activity to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices.

Claim 3

The arbitration circuit as recited in claim 1 wherein said tabulation circuit comprises a counting circuit adapted to change state when said request for designation is made.

Claim 4

The arbitration circuit as recited in claim 1 wherein said tabulation circuit comprises a plurality of counting circuits corresponding to each of said plurality of devices.

Claim 5

The arbitration circuit as recited in claim 1 wherein said tabulation circuit comprises a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation.

Claim 6

The arbitration circuit as recited in claim 1 further comprising a circuit for storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master.

Claim 7

The arbitration circuit as recited in claim 1 wherein said comparison circuit comprises a comparator for comparing numbers of times said each of said plurality of devices requests said designation as said bus master.

Claim 8

The arbitration circuit as recited in claim 1 further comprising a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.

Claim 9

The arbitration circuit as recited in claim 1 wherein said comparison circuit transmits a bus grant signal to a storage device, said bus grant signal representing a pending grant of said only one of said coinciding requests.

Claim 10

The arbitration circuit as recited in claim 1 wherein said computer system further comprises bus monitoring circuitry for controlling assertion of grants onto said bus.

Claim 11

The arbitration circuit as recited in claim 1 wherein said computer system is a personal computer (PC).

Claim 12

In a computer system having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, a method for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising the steps of: tabulating a relative request activity of each of said plurality of devices; and granting only one of said coinciding requests as a function of said relative request activity to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices.

Claim 13

In a computer system having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, a method for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising the steps of: tabulating a relative request activity of each of said plurality of devices; and granting only one of said coinciding requests as a function of said relative request activity to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices.

Claim 14

The method as recited in claim 11 wherein said step of tabulating comprises the step of changing a state of a counter when said request for designation is made.

Claim 15

The method as recited in claim 11 wherein said step of tabulating comprises the step of providing a plurality of counting circuits corresponding to each of said plurality of devices.

Claim 16

The method as recited in claim 11 wherein said step of tabulating comprises the step of providing a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation.

Claim 17

The method as recited in claim 11 further comprising the step of storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master.

Claim 18

The method as recited in claim 11 wherein said step of granting comprises the step of providing a comparator for comparing numbers of times said each of said plurality of devices requests said designation as said bus master.

Claim 19

The method as recited in claim 11 further comprising the step of providing a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.

Claim 20

The method as recited in claim 11 further comprising the step of transmitting a bus grant signal to a storage device, said bus grant signal representing a pending grant of said only one of said coinciding requests.

Claim 21

The method as recited in claim 11 further comprising the step of controlling assertion of grants onto said bus.

Claim 22

The method as recited in claim 11 wherein said computer system is a personal computer (PC).

Claim 23

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, an arbitration circuit for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising: a tabulation circuit for counting a relative number of times each of said plurality of devices requests said designation as said bus master; a comparison circuit coupled to said tabulation circuit for granting only one of said coinciding requests as a function of said relative number of times and comprising a comparator for comparing numbers of times said each of said plurality of devices requests said designation as said bus master to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices; a storage circuit for storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and bus monitoring circuitry for controlling assertion of grants onto said bus.

Claim 24

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, an arbitration circuit for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising: a tabulation circuit for counting a relative number of times each of said plurality of devices requests said designation as said bus master; a comparison circuit coupled to said tabulation circuit for granting only one of said coinciding requests as a function of said relative number of times and comprising a comparator for comparing numbers of times said each of said plurality of devices requests said designation as said bus master to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices; a storage circuit for storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and bus monitoring circuitry for controlling assertion of grants onto said bus.

Claim 25

The arbitration circuit as recited in claim 21 wherein said tabulation circuit comprises a counting circuit adapted to change state when said request for designation is made.

Claim 26

The arbitration circuit as recited in claim 21 wherein said tabulation circuit comprises a plurality of counting circuits corresponding to each of said plurality of devices.

Claim 27

The arbitration circuit as recited in claim 21 wherein said tabulation circuit comprises a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation.

Claim 28

The arbitration circuit as recited in claim 21 further comprising a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.

Claim 29

The arbitration circuit as recited in claim 21 wherein said comparison circuit transmits a bus grant signal to a storage device, said bus grant signal representing a pending grant of said only one of said coinciding requests.

Claim 30

The arbitration circuit as recited in claim 21 wherein said initial arbitration values are loaded into said storage circuit via a port coupled to said bus.

Claim 31

The arbitration circuit as recited in claim 21 wherein said storage circuit is embodied in said tabulation circuit.

Claim 32

The arbitration circuit as recited in claim 21 wherein a port coupled to said tabulation circuit allows said relative number of times each of said plurality of devices requests said designation as said bus master to be read from said tabulation circuit.

Claim 33

The arbitration circuit as recited in claim 21 wherein a deadlock circuit coupled to said tabulation circuit comprises a plurality of comparators for comparing predetermined priorities among said plurality of devices to thereby determine which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.

Claim 34

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, a method for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising the steps of: counting a relative number of times each of said plurality of devices requests said designation as said bus master; providing a comparator for comparing numbers of times said each of said plurality of devices requests said designation as said bus master; granting only one of said coinciding requests as a function of said relative number of times to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices; storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and controlling assertion of grants onto said bus.

Claim 35

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, a method for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising the steps of: counting a relative number of times each of said plurality of devices requests said designation as said bus master; providing a comparator for comparing numbers of times said each of said plurality of devices requests said designation as said bus master; granting only one of said coinciding requests as a function of said relative number of times to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices; storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and controlling assertion of grants onto said bus.

Claim 36

The method as recited in claim 31 wherein said step of counting comprises the step of changing a state of a counter when said request for designation is made.

Claim 37

The method as recited in claim 31 wherein said step of counting comprises the step of providing a plurality of counting circuits corresponding to each of said plurality of devices.

Claim 38

The method as recited in claim 31 wherein said step of counting comprises the step of providing a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation.

Claim 39

The method as recited in claim 31 further comprising the step of providing a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.

Claim 40

The method as recited in claim 31 further comprising the step of transmitting a bus grant signal to a storage device, said bus grant signal representing a pending grant of said only one of said coinciding requests.

Claim 41

The method as recited in claim 31 further comprising the step of loading said initial arbitration values into a storage circuit via a port coupled to said bus.

Claim 42

The method as recited in claim 31 wherein said step of storing comprises the step of embodying a storage circuit in a tabulation circuit.

Claim 43

The method as recited in claim 31 further comprising the step of reading said relative number of times each of said plurality of devices requests said designation as said bus master.

Claim 44

The method as recited in claim 31 further comprising the step of providing a plurality of comparators for comparing predetermined priorities among said plurality of devices to thereby determine which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.

Claim 45

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, an arbitration circuit for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising: a tabulation circuit for counting a relative number of times each of said plurality of devices requests said designation as said bus master and comprising a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation; a comparison circuit coupled to said tabulation circuit for granting only one of said coinciding requests as a function of said relative number of times and comprising a comparator for comparing a state of said first and second counting circuits to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said first and second devices; a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times; a storage circuit for storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and bus monitoring circuitry for controlling assertion of grants onto said bus.

Claim 46

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, an arbitration circuit for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising: a tabulation circuit for counting a relative number of times each of said plurality of devices requests said designation as said bus master and comprising a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation; a comparison circuit coupled to said tabulation circuit for granting only one of said coinciding requests as a function of said relative number of times and comprising a comparator for comparing a state of said first and second counting circuits to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said first and second devices; a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times; a storage circuit for storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and bus monitoring circuitry for controlling assertion of grants onto said bus.

Claim 47

The arbitration circuit as recited in claim 41 wherein said comparison circuit transmits a bus grant signal to a storage device, said bus grant signal representing a pending grant of said only one of said coinciding requests.

Claim 48

The arbitration circuit as recited in claim 41 wherein said initial arbitration values are loaded into said storage circuit via a port coupled to said bus.

Claim 49

The arbitration circuit as recited in claim 41 wherein a port coupled to said tabulation circuit allows said relative number of times each of said plurality of devices requests said designation as said bus master to be read from said tabulation circuit.

Claim 50

The arbitration circuit as recited in claim 41 wherein a deadlock circuit coupled to said tabulation circuit comprises a plurality of comparators for comparing predetermined priorities among said plurality of devices to thereby determine which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.

Claim 51

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, a method for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising the steps of: counting a relative number of times each of said plurality of devices requests said designation as said bus master, said step of counting comprising the step of providing a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation; providing a comparator for comparing a state of said first and second counting circuits; granting only one of said coinciding requests as a function of said state of said first and second counting circuits to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices; providing a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times; providing a storage circuit for storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and controlling assertion of grants onto said bus.

Claim 52

In a personal computer (PC) having a plurality of devices coupled to a bus, said plurality of devices having a bus master mode allowing a selected one of said devices to function as a bus master and adapted to request designation as a bus master, a method for determining which one of said plurality of devices is to function as said bus master when two of said plurality of devices coincidentally request said designation, comprising the steps of: counting a relative number of times each of said plurality of devices requests said designation as said bus master, said step of counting comprising the step of providing a first counting circuit corresponding to a first device of said plurality of devices and a second counting circuit corresponding to a second device of said plurality of devices, said first counting circuit incrementing and said second counting circuit decrementing when said first device requests said designation; providing a comparator for comparing a state of said first and second counting circuits; granting only one of said coinciding requests as a function of said state of said first and second counting circuits to thereby allow a bus master priority level between said plurality of devices to change as a function of an activity of said plurality of devices; providing a deadlock circuit for determining which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times; providing a storage circuit for storing initial arbitration values, said initial arbitration values initially determining which of said plurality of devices is to function as said bus master; and controlling assertion of grants onto said bus.

Claim 53

The method as recited in claim 46 further comprising the step of transmitting a bus grant signal to a storage device, said bus grant signal representing a pending grant of said only one of said coinciding requests.

Claim 54

The method as recited in claim 46 further comprising the step of loading said initial arbitration values into said storage circuit via a port coupled to said bus.

Claim 55

The method as recited in claim 46 further comprising the step of reading said relative number of times each of said plurality of devices requests said designation as said bus master.

Claim 56

The method as recited in claim 46 further comprising the step of providing a plurality of comparators for comparing predetermined priorities among said plurality of devices to thereby determine which one of said plurality of devices is to function as said bus master when said two of said plurality of devices have requested said designation as said bus master an equal relative number of times.