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US5561084A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making an interconnection structure of a semiconductor device

Assignee: Renesas Electronics Corp
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Filing: 1995-06-02
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Granted: 1996-10-01
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Expires: 2015-06-02
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Abstract

Abstract A first aluminum interconnection layer includes an aluminum alloy layer 12 and an upper metal layer 13 containing refractory metal. A second aluminum layer 15 is in contact with a surface of upper metal layer 13 through a through-hole 19. A thickness t2 of a contact portion 132 of upper metal layer 13 is smaller than a thickness t1 of a non-contact portion 131. In an interconnection structure for a semiconductor integrated circuit device, the increase in electric resistance by the through-hole is suppressed, and also effects achieved by layer 13 containing refractory metal forming the most upper portion of first aluminum interconnection layer 1A are maintained.

Inventors

  • 👤 Yoshifumi Takata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 23:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10W20/425

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 102 words
A method of manufacturing an interconnection structure for a semiconductor device, comprising the steps of: forming a first interconnection layer comprising upper and lower conductive layers, one on top of the other; forming an insulating layer on said first interconnection layer; forming a through-hole extending completely through said insulating layer and into but not through said upper conductive layer by selectively removing said insulating layer, and said upper conductive layer; and forming a second interconnection layer on said insulating layer, said second interconnection layer extending through said through-hole so as to be in contact with a surface of said upper conductive layer.
Claim 2
Independent Claim 102 words
A method of manufacturing an interconnection structure for a semiconductor device, comprising the steps of: forming a first interconnection layer comprising upper and lower conductive layers, one on top of the other; forming an insulating layer on said first interconnection layer; forming a through-hole extending completely through said insulating layer and into but not through said upper conductive layer by selectively removing said insulating layer, and said upper conductive layer; and forming a second interconnection layer on said insulating layer, said second interconnection layer extending through said through-hole so as to be in contact with a surface of said upper conductive layer.
Claim 3
Dependent Claim 33 words
The manufacturing method of an interconnection structure for a semiconductor device according to claim 1, wherein said step forming the trough-hole includes the step of removing said upper conductive layer by anisotropic etching.
Claim 4
Dependent Claim 31 words
The manufacturing method of an interconnection structure for a semiconductor device according to claim 2, wherein said step forming the trough-hole includes the step of controlling time of said anisotropic etching.
Claim 5
Dependent Claim 53 words
The manufacturing method of an interconnection structure for a semiconductor device according to claim 2, wherein said step forming the through-hole includes the step of using a gas of at least one selected from a group consisting of SF 6 , SiCl 4 , Cl 2 and CF 4 as an etching gas.

References Cited (Backward Citations)

US3562604A Cited
US4556897A Cited
US4900695A Cited
US4965226A Cited
US5082801A Cited
US5422312A Cited
US5470790A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-10-01 2000-04-01 2000-10-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-10-01 2004-04-01 2004-10-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-10-01 2008-04-01 2008-10-01 $7700.00 Window Closed / Lapsed

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