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US5561784A
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Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses
Assignee: Supercomputer Systems LP
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Filing: 1994-06-29
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Granted: 1996-10-01
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Expires: 2014-06-29
Abstract
Abstract A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
Inventors
- 👤 Steve S. Chen
- 👤 Frederick J. Simmons
- 👤 George A. Spix
- 👤 Jimmie R. Wilson
- 👤 Edward C. Miller
- 👤 Roger E. Eckert
- 👤 Douglas R. Beard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:49
CPC Classifications
G; G06; G06F; G06F17/00; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30087; G06F11/00; G06F11/36; G06F11/362; G06F11/3632; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17381; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8092; G06F8/00; G06F8/40; G06F8/41; G06F8/43; G06F8/433; G06F8/45; G06F9/30007; G06F9/30021; G06F9/3004; G06F9/30094; G06F9/30098; G06F9/3012; G06F9/3013; G06F9/30138; G06F9/30141; G06F9/30145; G06F9/30149; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3814; G06F9/3816; G06F9/3824; G06F9/3826; G06F9/3828; G06F9/3834; G06F9/3836; G06F9/3838; G06F9/3842; G06F9/3846; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3867; G06F9/3875; G06F9/3885
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
266 words
A method of accessing memory of a multiprocessor system using a plurality of segment mapping registers to minimize memory system wait times a processor may incur in accessing a particular memory section and subsection, each processor having one or more logical address spaces used by instructions and data, wherein each logical address space is divided into one or more variable-sized segments which are mapped into a physical address space of the memory, wherein each segment mapping register defines a start-and-end range for one variable-sized segment each start-and-end range having a start address and an end address, the method comprising the steps of: receiving a memory reference request from a processor in a form of a logical address; determining whether the logical address is within one of the start-and-end ranges for one of the variable-sized segments as defined by said segment mapping registers; generating an address translation exception if the logical address is not within any one of the start-and-end ranges as defined by the segment mapping registers; relocating said logical address to a physical address using a displacement value in one of said segment mapping registers to generate the physical address; dividing the physical address into most significant bits representing higher-order physical address bits and least-significant bits representing lower-order physical address bits such that the least significant bits are a lowest address increment available to the processor; mapping the lower order physical address bits into interleaved memory sections; mapping the higher order physical address bits into interleaved subsections of the interleaved memory sections; and retrieving a memory reference and returning said memory reference to the processor.
Claim 2
Independent Claim
266 words
A method of accessing memory of a multiprocessor system using a plurality of segment mapping registers to minimize memory system wait times a processor may incur in accessing a particular memory section and subsection, each processor having one or more logical address spaces used by instructions and data, wherein each logical address space is divided into one or more variable-sized segments which are mapped into a physical address space of the memory, wherein each segment mapping register defines a start-and-end range for one variable-sized segment each start-and-end range having a start address and an end address, the method comprising the steps of: receiving a memory reference request from a processor in a form of a logical address; determining whether the logical address is within one of the start-and-end ranges for one of the variable-sized segments as defined by said segment mapping registers; generating an address translation exception if the logical address is not within any one of the start-and-end ranges as defined by the segment mapping registers; relocating said logical address to a physical address using a displacement value in one of said segment mapping registers to generate the physical address; dividing the physical address into most significant bits representing higher-order physical address bits and least-significant bits representing lower-order physical address bits such that the least significant bits are a lowest address increment available to the processor; mapping the lower order physical address bits into interleaved memory sections; mapping the higher order physical address bits into interleaved subsections of the interleaved memory sections; and retrieving a memory reference and returning said memory reference to the processor.
Claim 3
Dependent Claim
24 words
The method according to claim 1 wherein the step of generating an address translation exception includes the step of halting said memory reference request.
Claim 4
Independent Claim
225 words
A method for accessing memory of a multiprocessor system, said multiprocessor system having a plurality of processors, each one of said processors having one or more logical address spaces used by instructions and data wherein each logical address space is divided into one or more variable-sized segments which are mapped into a physical address space of the memory, each one of said processors having a plurality of segment mapping registers, each segment mapping register defining a variable-sized address range and a translation map, said method comprising the steps of: receiving a memory reference request from a processor, said memory reference request including a logical address; determining whether said logical address is within said variable-sized address range defined by one of said segment mapping registers; generating an address translation exception if said logical address is not within any of said address ranges defined by said segment mapping registers; producing a physical address using said logical address and said translation map from one of said segment mapping registers; dividing said physical address into most-significant bits representing higher-order physical address bits and least-significant bits representing lower-order physical address bits; mapping said lower-order physical address bits into interleaved memory sections; mapping said higher-order physical address bits into interleaved subsections of said interleaved memory sections; and accessing memory using said lower-order physical address bits and said higher-order physical address bits.
Claim 5
Independent Claim
225 words
A method for accessing memory of a multiprocessor system, said multiprocessor system having a plurality of processors, each one of said processors having one or more logical address spaces used by instructions and data wherein each logical address space is divided into one or more variable-sized segments which are mapped into a physical address space of the memory, each one of said processors having a plurality of segment mapping registers, each segment mapping register defining a variable-sized address range and a translation map, said method comprising the steps of: receiving a memory reference request from a processor, said memory reference request including a logical address; determining whether said logical address is within said variable-sized address range defined by one of said segment mapping registers; generating an address translation exception if said logical address is not within any of said address ranges defined by said segment mapping registers; producing a physical address using said logical address and said translation map from one of said segment mapping registers; dividing said physical address into most-significant bits representing higher-order physical address bits and least-significant bits representing lower-order physical address bits; mapping said lower-order physical address bits into interleaved memory sections; mapping said higher-order physical address bits into interleaved subsections of said interleaved memory sections; and accessing memory using said lower-order physical address bits and said higher-order physical address bits.
Claim 6
Dependent Claim
30 words
The method according to claim 3 wherein said translation map comprises a displacement, and wherein the step of producing a physical address includes adding said logical address to said displacement.
Claim 7
Dependent Claim
24 words
The method according to claim 3 wherein the step of generating an address translation exception includes the step of halting said memory reference request.
Claim 8
Dependent Claim
24 words
The method according to claim 4 wherein the step of generating an address translation exception includes the step of halting said memory reference request.
Claim 9
Independent Claim
251 words
An apparatus for accessing memory of a multiprocessor system, said multiprocessor system having a plurality of processors, each one of said processors having one or more logical address spaces used by instructions and data, wherein each logical address space is divided into one or more variable-sized segments which are mapped into a physical address space of the memory, each one of said processors having a plurality of segment mapping registers, each segment mapping register defining a variable-sized address range and a translation mapping, said apparatus comprising: means for receiving a memory reference request from a processor, said memory reference request including a logical address; means for determining whether the logical address is within the variable-sized address range defined by one of said segment mapping registers; means for generating an address translation exception if the logical address is not within any of the address ranges defined by the segment mapping registers; means for producing a physical address using the logical address and a translation mapping from one of said segment mapping registers; means for dividing the physical address into most-significant bits representing higher-order physical address bits and least-significant bits representing lower-order physical address bits such that the least-significant bits are the lowest address increment available to the processor; means for mapping the lower-order physical address bits into interleaved memory sections; means for mapping the higher-order physical address bits into interleaved subsections of the interleaved memory sections; and means for accessing memory using the lower-order physical address bits and higher-order physical address bits.
Claim 10
Independent Claim
251 words
An apparatus for accessing memory of a multiprocessor system, said multiprocessor system having a plurality of processors, each one of said processors having one or more logical address spaces used by instructions and data, wherein each logical address space is divided into one or more variable-sized segments which are mapped into a physical address space of the memory, each one of said processors having a plurality of segment mapping registers, each segment mapping register defining a variable-sized address range and a translation mapping, said apparatus comprising: means for receiving a memory reference request from a processor, said memory reference request including a logical address; means for determining whether the logical address is within the variable-sized address range defined by one of said segment mapping registers; means for generating an address translation exception if the logical address is not within any of the address ranges defined by the segment mapping registers; means for producing a physical address using the logical address and a translation mapping from one of said segment mapping registers; means for dividing the physical address into most-significant bits representing higher-order physical address bits and least-significant bits representing lower-order physical address bits such that the least-significant bits are the lowest address increment available to the processor; means for mapping the lower-order physical address bits into interleaved memory sections; means for mapping the higher-order physical address bits into interleaved subsections of the interleaved memory sections; and means for accessing memory using the lower-order physical address bits and higher-order physical address bits.
Claim 11
Dependent Claim
32 words
The apparatus according to claim 7 wherein said translation map comprises a displacement, and wherein the means for producing a physical address includes means for adding said logical address to said displacement.
Claim 12
Dependent Claim
23 words
The apparatus according to claim 7 wherein the means for generating an address translation exception includes means for halting said memory reference request.
Claim 13
Dependent Claim
23 words
The apparatus according to claim 8 wherein the means for generating an address translation exception includes means for halting said memory reference request.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |