Patent US6689803B2 successfully refreshed from Google Patents.
Patent US5564022A successfully refreshed from Google Patents.
US5564022A
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Method and apparatus for automatically inserting clock buffers into a logic block to reduce clock skew
Assignee: Intel Corp
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Filing: 1994-02-09
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Granted: 1996-10-08
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Expires: 2014-02-09
Abstract
Abstract A method and apparatus for inserting clock buffers to reduce clock skew in a logic block in which the proper placement of the cells within the logic block is first determined. Given this cell placement and the location of the local clock lines, the placement of clock buffers within the logic block is determined such that the clock buffers are in close proximity to the local clock lines. Routing is then performed to connect the clock buffers to their corresponding clock trunks and the cells requiring clock signals to their corresponding clock buffers. The performance of the logic block is then evaluated. If the performance does not satisfy a predetermined minimum threshold then the cells are modified to satisfy the minimum threshold, or come closer to attaining it. The clock buffers are removed, and the proper placement of the new cells within the logic block is determined. Given this new cell placement a new set of clock buffers is placed and a new routing is created. The performance is then re-evaluated and, if the minimum threshold still has not been attained, the above process is repeated.
Inventors
- 👤 Goutam Debnath
- 👤 Kelly J. Fitzpatrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:43
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F30/00; G06F30/30; G06F30/39; G06F30/394
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
88 words
A method for automatically reducing clock skew in a logic block having a plurality of cells, the method comprising the steps of: (a) determining a placement of said plurality of cells within said logic block; (b) determining a placement of a plurality of clock buffers within said logic block such that each clock buffer of said plurality of clock buffers is located in close proximity to a clock line; and (c) determining a routing between said plurality of clock buffers, said plurality of cells and said clock line.
Claim 2
Independent Claim
88 words
A method for automatically reducing clock skew in a logic block having a plurality of cells, the method comprising the steps of: (a) determining a placement of said plurality of cells within said logic block; (b) determining a placement of a plurality of clock buffers within said logic block such that each clock buffer of said plurality of clock buffers is located in close proximity to a clock line; and (c) determining a routing between said plurality of clock buffers, said plurality of cells and said clock line.
Claim 3
Dependent Claim
24 words
A method for reducing clock skew as claimed in claim 1 further comprising the step of: (d) determining the performance of said logic block.
Claim 4
Dependent Claim
70 words
A method for reducing clock skew as claimed in claim 2 further comprising the steps of: (e) removing said plurality of clock buffers from said logic block if said performance is below a predetermined minimum threshold; (f) modifying at least one cell of said plurality of cells if said performance is below said minimum threshold; and (g) repeating steps (a) through (g) if said performance is below said minimum threshold.
Claim 5
Dependent Claim
44 words
A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of a plurality of clock buffers comprises locating each clock buffer of said plurality of clock buffers in a closest available position to a clock line.
Claim 6
Dependent Claim
34 words
A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of said plurality of cells comprises receiving a description of connectivity between a plurality of cells.
Claim 7
Dependent Claim
36 words
A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of a plurality of clock buffers further comprises receiving a description of the location of said clock line.
Claim 8
Dependent Claim
32 words
A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of said plurality of cells comprises placing said cells within a plurality of rows.
Claim 9
Dependent Claim
63 words
A method for reducing clock skew as claimed in claim 1 wherein said step of determining the placement of a plurality of clock buffers further comprises placing a first set of clock buffers of a first clock buffer type corresponding to a first clock and placing a second set of clock buffers of a second clock buffer type corresponding to a second clock.
Claim 10
Dependent Claim
51 words
A method for reducing clock skew as claimed in claim 1 wherein said step of determining the placement of said plurality of clock buffers further comprises placing a first set of clock buffers corresponding to a first clock line and placing a second clock buffer corresponding to a second clock line.
Claim 11
Dependent Claim
67 words
A method for reducing clock skew as claimed in claim 1 wherein said step of determining said routing comprises coupling each buffer of said plurality of buffers to said clock line and coupling each cell of said plurality of cells requiring a clock signal to a buffer of said plurality of buffers such that no cell requiring a clock signal is directly coupled to said clock line.
Claim 12
Independent Claim
123 words
A method for automatically inserting buffers into a logic block having a plurality of cells, the method comprising the steps of: (a) determining a placement of a plurality of cells within said logic block; (b) determining a placement of a plurality of buffers within said logic block; (c) determining a routing between said plurality of buffers, said plurality of cells and said clock line; (d) determining the performance of said logic block; (e) removing said plurality of buffers from said logic block if said performance is below a predetermined minimum threshold; (f) modifying a cell of said plurality of cells if said performance is below said minimum threshold; and (g) repeating steps (a) through (g) if said performance is below said minimum threshold.
Claim 13
Independent Claim
123 words
A method for automatically inserting buffers into a logic block having a plurality of cells, the method comprising the steps of: (a) determining a placement of a plurality of cells within said logic block; (b) determining a placement of a plurality of buffers within said logic block; (c) determining a routing between said plurality of buffers, said plurality of cells and said clock line; (d) determining the performance of said logic block; (e) removing said plurality of buffers from said logic block if said performance is below a predetermined minimum threshold; (f) modifying a cell of said plurality of cells if said performance is below said minimum threshold; and (g) repeating steps (a) through (g) if said performance is below said minimum threshold.
Claim 14
Dependent Claim
41 words
The method of claim 11 wherein said step (b) comprises determining a placement of a plurality of buffers within said logic block such that each clock buffer of said plurality of buffers is located in close proximity to a clock line.
Claim 15
Dependent Claim
27 words
The method of claim 11 wherein said step (b) comprises locating each buffer of said plurality of buffers in the closest available position to a clock line.
Claim 16
Dependent Claim
18 words
The method of claim 11 wherein said step (a) comprises placing said cells within a plurality of rows.
Claim 17
Dependent Claim
29 words
The method of claim 11 wherein said step (b) comprises placing a first buffer of a first buffer type and placing a second buffer of a second buffer type.
Claim 18
Dependent Claim
32 words
The method of claim 11 wherein said step (b) comprises placing a first buffer corresponding to a first clock line and placing a second clock buffer corresponding to a second clock line.
Claim 19
Dependent Claim
58 words
The method of claim 11 wherein said step (c) comprises coupling each buffer of said plurality of buffers to said clock line and coupling each cell of said plurality of cells requiring a clock signal to a buffer of said plurality of buffers such that no cell requiring a clock signal is directly coupled to said clock line.
Claim 20
Dependent Claim
22 words
The method of claim 11 wherein said step (g) comprises determining a placement of a buffer and repeating steps (c) through (g).
Claim 21
Independent Claim
165 words
An apparatus for inserting clock buffers into a logic block having a plurality of cells to reduce clock skew, the apparatus comprising: a bus; a memory device which stores a set of available clock buffers, wherein the memory device is coupled to the bus; and a processor, coupled to the bus, for determining a placement of a plurality of cells within said logic block, determining a placement of a plurality of clock buffers selected from the set of available clock buffers within said logic block such that each clock buffer of said plurality of clock buffers is located in close proximity to a clock line, determining the routing between said plurality of clock buffers, said plurality of cells and said clock line, determining the performance of said logic block, removing said plurality of clock buffers from said logic block if said performance is below a predetermined minimum threshold, and modifying a cell of said plurality of cells if said performance is below said minimum threshold.
Claim 22
Independent Claim
165 words
An apparatus for inserting clock buffers into a logic block having a plurality of cells to reduce clock skew, the apparatus comprising: a bus; a memory device which stores a set of available clock buffers, wherein the memory device is coupled to the bus; and a processor, coupled to the bus, for determining a placement of a plurality of cells within said logic block, determining a placement of a plurality of clock buffers selected from the set of available clock buffers within said logic block such that each clock buffer of said plurality of clock buffers is located in close proximity to a clock line, determining the routing between said plurality of clock buffers, said plurality of cells and said clock line, determining the performance of said logic block, removing said plurality of clock buffers from said logic block if said performance is below a predetermined minimum threshold, and modifying a cell of said plurality of cells if said performance is below said minimum threshold.
Claim 23
Dependent Claim
46 words
An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining a placement of a plurality of clock buffers is also for locating each clock buffer of said plurality of clock buffers in a closest available position to a clock line.
Claim 24
Dependent Claim
31 words
An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining the placement of said plurality of cells places said cells within a plurality of rows.
Claim 25
Dependent Claim
64 words
An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining the placement of said plurality of clock buffers is also for placing a first set of clock buffers of a first clock buffer type corresponding to a first clock and placing a second set of clock buffers of a second clock buffer type corresponding to a second clock.
Claim 26
Dependent Claim
52 words
An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining the placement of said plurality of clock buffers is also for placing a first set of clock buffers corresponding to a first clock line and placing a second clock buffer corresponding to a second clock line.
Claim 27
Dependent Claim
70 words
An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining said routing is also for coupling each buffer of said plurality of buffers to said clock line and coupling each cell of said plurality of cells which requires a clock signal to a buffer of said plurality of buffers such that no cell requiring a clock signal is directly coupled to said clock line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |