Microprocessor for inserting a bus cycle in an instruction set to output an internal information for an emulation

Claim 1

An in-circuit emulator system having a trace memory for storing a signal on a bus for debugging a program, a break point control unit for stopping a trace to interrupt the program and a microprocessor for prefetching a plurality of instructions, said emulation microprocessor comprising: an instruction buffer for holding a plurality of instructions fetched from an external memory; an instruction decoder, coupled to said instruction buffer, for decoding said instructions, and for providing a decoded result; an instruction execution unit coupled to said instruction decoder, including an operation device and registers, and for executing said instructions; an address controller, coupled to said instruction execution unit, and including an instruction fetch pointer for identifying an address; a bus control circuit, coupled to said instruction buffer, to said instruction execution unit and to said address controller, having a bus cycle change circuit, said bus cycle change circuit having a function for inserting a bus cycle in said plurality of instructions after completion of a first instruction execution and before a next instruction execution for outputting internal information of said microprocessor when a special bus cycle request signal from said break point control unit and an internal control signal of a predetermined level are provided to said cycle change circuit and while continuing a sequence of said plurality of instructions so that the outputting of the internal information for program debugging is done without deteriorating real time behavior of the microprocessor; wherein said instruction buffer, said instruction decoder, said instruction execution unit, said address controller, and said bus control circuit, all are constructed in a single semiconductor device.