Method of manufacturing a self-aligned bit line contact to a semiconductor device

Claim 1

A method of manufacturing a semiconductor device, comprising the steps of: forming a plurality of gate electrodes on a silicon substrate on which an isolation layer is formed, thereafter forming a first insulating layer on said gate electrodes, respectively; forming a drain region and a source region on said substrate using openings between said gate electrodes; sequentially forming a second insulating layer and conductive layer on said first insulating layer including said drain region and said source region; forming a third insulating layer on said conductive layer, and forming a first photoresist pattern on said third insulating layer so that a portion of said third insulating layer corresponding to said drain region is exposed; etching an exposed portion of said third insulating layer; sequentially etching said conductive layer and said second insulating layer, exposed by etching said third insulating layer, to expose said drain region, thereby forming a first contact hole for a bit line; removing said first photoresist pattern, and forming a first insulating spacer on the inner walls of said first contact hole; forming a bit line connected to said drain region by filling said first contact hole with a conductive material, with said bit line forming on said third insulating layer; etching a portion of said bit line so that a portion of said third insulating layer corresponding to said source region is exposed; forming a fourth insulating layer on said bit line including an exposed portion of said third insulating layer, and forming a second photoresist pattern on said fourth insulating layer so that a portion of said fourth insulating layer corresponding to said source region is exposed; sequentially etching said fourth and third insulating layers, exposed by said photoresist pattern; sequentially etching said conductive layer, said bit line and said second insulating layer, exposed by said fourth and third insulating layers, to expose said source region, thereby forming a second contact hole for a charge storage electrode; removing said second photoresist pattern, and forming a second insulating spacer on the inner walls of said second contact hole; and forming a bit line connected to said source region by filling said second contact hole.

Claim 2

A method of manufacturing a semiconductor device, comprising the steps of: forming a plurality of gate electrodes on a silicon substrate on which an isolation layer is formed, thereafter forming a first insulating layer on said gate electrodes, respectively; forming a drain region and a source region on said substrate using openings between said gate electrodes; sequentially forming a second insulating layer and conductive layer on said first insulating layer including said drain region and said source region; forming a third insulating layer on said conductive layer, and forming a first photoresist pattern on said third insulating layer so that a portion of said third insulating layer corresponding to said drain region is exposed; etching an exposed portion of said third insulating layer; sequentially etching said conductive layer and said second insulating layer, exposed by etching said third insulating layer, to expose said drain region, thereby forming a first contact hole for a bit line; removing said first photoresist pattern, and forming a first insulating spacer on the inner walls of said first contact hole; forming a bit line connected to said drain region by filling said first contact hole with a conductive material, with said bit line forming on said third insulating layer; etching a portion of said bit line so that a portion of said third insulating layer corresponding to said source region is exposed; forming a fourth insulating layer on said bit line including an exposed portion of said third insulating layer, and forming a second photoresist pattern on said fourth insulating layer so that a portion of said fourth insulating layer corresponding to said source region is exposed; sequentially etching said fourth and third insulating layers, exposed by said photoresist pattern; sequentially etching said conductive layer, said bit line and said second insulating layer, exposed by said fourth and third insulating layers, to expose said source region, thereby forming a second contact hole for a charge storage electrode; removing said second photoresist pattern, and forming a second insulating spacer on the inner walls of said second contact hole; and forming a bit line connected to said source region by filling said second contact hole.

Claim 8

The method of claim is wherein said first insulating spacer is formed by oxidizing said conductive layer exposed on the inner walls of the first contact hole.

Claim 10

The method of claim is wherein said third insulating layer exposed by said first photoresist pattern is etched by an anisotropic etching method.

Claim 16

A method of manufacturing a semiconductor device, comprising the steps of: forming a plurality of gate electrodes on a silicon substrate on which an isolation layer is formed, thereafter forming a first insulating layer on said gate electrodes, respectively; forming a drain region and a source region on said substrate using openings between said gate electrodes; sequentially forming a second insulating layer and conductive layer on said first insulating layer including said drain region and said source region; forming a third insulating layer on said conductive layer, and forming a first photoresist pattern on said third insulating layer so that a portion of said third insulating layer corresponding to said drain region is exposed; etching an exposed portion of said third insulating layer; sequentially etching said conductive layer and said second insulating layer, exposed by etching said third insulating layer, to expose said drain region, thereby forming a first contact hole for a bit line; removing said first photoresist pattern, and forming a first insulating spacer on the inner walls of said first contact hole; forming a bit line connected to said drain region by filling said first contact hole with a conductive material, with said bit line forming on said third insulating layer; etching a portion of said bit line so that a portion of said third insulating layer corresponding to said source region is exposed; forming a fourth insulating layer on said bit line including an exposed portion of said third insulating layer, and forming a second photoresist pattern on said fourth insulating layer so that a portion of said fourth insulating layer corresponding to said source region is exposed; etching an exposed portion of the fourth insulating layer to expose said bit line, thereafter etching an exposed portion of said bit line; sequentially etching residual portion of said fourth insulating layer and an exposed portion of said third insulating layer; sequentially etching said conductive layer, and said second insulating layer, exposed by etching of said fourth and third insulating layers, to expose said source region, thereby forming a second contact hole for a charge storage electrode; removing said second photoresist pattern, and forming a second insulating spacer on the inner walls of said second contact hole; and forming a bit line connected to said source region by filling said second contact hole.

Claim 17

A method of manufacturing a semiconductor device, comprising the steps of: forming a plurality of gate electrodes on a silicon substrate on which an isolation layer is formed, thereafter forming a first insulating layer on said gate electrodes, respectively; forming a drain region and a source region on said substrate using openings between said gate electrodes; sequentially forming a second insulating layer and conductive layer on said first insulating layer including said drain region and said source region; forming a third insulating layer on said conductive layer, and forming a first photoresist pattern on said third insulating layer so that a portion of said third insulating layer corresponding to said drain region is exposed; etching an exposed portion of said third insulating layer; sequentially etching said conductive layer and said second insulating layer, exposed by etching said third insulating layer, to expose said drain region, thereby forming a first contact hole for a bit line; removing said first photoresist pattern, and forming a first insulating spacer on the inner walls of said first contact hole; forming a bit line connected to said drain region by filling said first contact hole with a conductive material, with said bit line forming on said third insulating layer; etching a portion of said bit line so that a portion of said third insulating layer corresponding to said source region is exposed; forming a fourth insulating layer on said bit line including an exposed portion of said third insulating layer, and forming a second photoresist pattern on said fourth insulating layer so that a portion of said fourth insulating layer corresponding to said source region is exposed; etching an exposed portion of the fourth insulating layer to expose said bit line, thereafter etching an exposed portion of said bit line; sequentially etching residual portion of said fourth insulating layer and an exposed portion of said third insulating layer; sequentially etching said conductive layer, and said second insulating layer, exposed by etching of said fourth and third insulating layers, to expose said source region, thereby forming a second contact hole for a charge storage electrode; removing said second photoresist pattern, and forming a second insulating spacer on the inner walls of said second contact hole; and forming a bit line connected to said source region by filling said second contact hole.