Antifuse with silicon spacers

Claim 2

An antifuse structure in an integrated circuit device, said integrated circuit device formed within and on a semiconductor substrate, said antifuse structure comprising: a first metal layer on a first insulating layer over said substrate; a first refractory metal layer on said first metal layer; a second insulating layer over said first metal layer and said first refractory metal layer, said second insulating layer having an aperture exposing said first refractory metal layer therein; an amorphous silicon layer in said aperture, said amorphous silicon layer having a first region on said first refractory metal layer and displaced from sides of said second insulating layer in said aperture, and a second region on said sides of said second insulating layer, said first region having substantially a first thickness, said second region having substantially a second thickness, said second thickness greater than said first thickness; a second refractory metal layer on said amorphous silicon layer; and a second metal layer on said second refractory metal layer; whereby, upon programming of said antifuse structure, a conducting link is formed in said first region of said amorphous silicon layer.

Claim 3

An antifuse structure as in claim 1 wherein said first region of said amorphous silicon layer is in the range of about 1,500 Å thick and said second region of said amorphous silicon layer is in the range of about 3,000 Å thick.

Claim 4

An antifuse structure in an integrated circuit device, said integrated circuit device formed within and on a semiconductor substrate, said antifuse structure comprising: a first metal interconnection layer on a first insulating layer over said substrate; a second insulating layer over said first metal interconnection layer and said first metal interconnection layer, said second insulating layer having an aperture therethrough to expose a top surface of said first metal interconnection layer to define sides of said second insulating layer in said aperture; a spacer region in said aperture, said spacer region on said sides of said second insulating layer in said aperture wherein said spacer region comprises nonconducting semiconductor material from the group consisting of amorphous silicon, undoped polysilicon, silicon dioxide, and silicon nitride; a programming layer in said aperture, said programming layer having a region on said first metal interconnection layer and displaced from sides of said second insulating layer in said aperture; and a second metal interconnection layer on said programming layer; whereby, upon programming of said antifuse structure, a conducting link is formed in said region of said programming layer.

Claim 5

An antifuse structure in an integrated circuit device, said integrated circuit device formed within and on a semiconductor substrate, said antifuse structure comprising: a first metal interconnection layer on a first insulating layer over said substrate; a second insulating layer over said first metal interconnection layer and said first metal interconnection layer, said second insulating layer having an aperture therethrough to expose a top surface of said first metal interconnection layer to define sides of said second insulating layer in said aperture; a spacer region in said aperture, said spacer region on said sides of said second insulating layer in said aperture wherein said spacer region comprises nonconducting semiconductor material from the group consisting of amorphous silicon, undoped polysilicon, silicon dioxide, and silicon nitride; a programming layer in said aperture, said programming layer having a region on said first metal interconnection layer and displaced from sides of said second insulating layer in said aperture; and a second metal interconnection layer on said programming layer; whereby, upon programming of said antifuse structure, a conducting link is formed in said region of said programming layer.

Claim 6

An antifuse structure as in claim 3 wherein both first and second metal interconnection layers comprise a refractory metal layer.

Claim 7

An antifuse structure as in claim 4 wherein said region of said programming layer is in the range of approximately 1000 Å thick.

Claim 8

An antifuse structure as in claim 3 wherein said spacer region comprises a nonconducting semiconductor material from the group consisting of amorphous silicon, undoped polysilicon, silicon dioxide and silicon nitride.

Claim 9

An antifuse structure as in claim 6 wherein said programming layer comprises nonconducting semiconductor material from the group consisting of amorphous silicon, undoped polysilicon, silicon dioxide and silicon nitride.

Claim 10

An antifuse structure as in claim 7 wherein said spacer region and said programming layer comprise the same material.

Claim 11

An antifuse structure as in claim 4 wherein said first metal interconnection layer comprises an etch stop layer overlying said refractory metal layer.

Claim 12

The antifuse structure of claim 9 wherein said etch stop layer comprises aluminum.

Claim 13

The antifuse structure of claim 10 wherein said etch stop layer has a thickness ranging from about 200 to 400 Å.

Claim 14

An antifuse structure as in claim 1 further comprising an etch stop layer on said first refractory metal layer.

Claim 15

The antifuse structure of claim 12 wherein said etch stop layer comprises aluminum.

Claim 16

The antifuse structure of claim 13 wherein said etch stop layer has a thickness ranging from about 200 to 400 Å.