Patent US5574933A successfully refreshed from Google Patents.
US5574933A
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Task flow computer architecture
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-10-26
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Granted: 1996-11-12
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Expires: 2014-10-26
Abstract
Abstract A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an instruction, a data element, and a pointer to another memory packet. Tasks are executed by following a linked list of memory packets. Transmission packets communicate instructions and register values along the linked list. A plurality of computer processes may be executed simultaneously.
Inventors
- 👤 Robert W. Horst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:39
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4494
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
365 words
A computer for executing a task, the task being segmented into a plurality of instructions to be executed sequentially, said computer comprising: (a) an interconnection network; (b) a first cell coupled to said interconnection network, said first cell including: a first receive queue coupled to said interconnection network for receiving a first incoming transmission packet containing a first instruction and a first link address, said first link address identifying a first memory packet and forming a portion of a linked list of memory packets specifying an order of execution; a first memory coupled to said first receive queue for storing said first memory packet, said first memory packet being selectively disposed in said first cell and including a second instruction, a first data element and a second link address, said second link address identifying a second memory packet and forming a portion of said linked list of memory packets specifying an order of execution; a bypass queue coupled to said first memory for outputting a second incoming transmission packet that addresses no memory packet residing in said first memory; a first arithmetic and logic unit (ALU) coupled to said first memory for executing said first instruction; means coupled to said first ALU for generating a first outgoing transmission packet containing said second instruction and a link field for storing said second link address; and (c) a second cell coupled to said first cell through said interconnection network, said second cell comprising: a second receive queue coupled to said interconnection network for receiving said first outgoing transmission packet; a second memory coupled to said second receive queue for storing said second memory packet, said second memory packet being selectively disposed in said second cell and including a third instruction, a second data element and a third link address, said third link address identifying a third memory packet and forming a portion of said linked list of memory packets specifying an order of execution; a second ALU coupled to said second memory for executing said second instruction stored in said first outgoing transmission packet; and means coupled to said second ALU for generating a second outgoing transmission packet containing said third instruction and said third link address.
Claim 2
Dependent Claim
365 words
A computer for executing a task, the task being segmented into a plurality of instructions to be executed sequentially, said computer comprising: (a) an interconnection network; (b) a first cell coupled to said interconnection network, said first cell including: a first receive queue coupled to said interconnection network for receiving a first incoming transmission packet containing a first instruction and a first link address, said first link address identifying a first memory packet and forming a portion of a linked list of memory packets specifying an order of execution; a first memory coupled to said first receive queue for storing said first memory packet, said first memory packet being selectively disposed in said first cell and including a second instruction, a first data element and a second link address, said second link address identifying a second memory packet and forming a portion of said linked list of memory packets specifying an order of execution; a bypass queue coupled to said first memory for outputting a second incoming transmission packet that addresses no memory packet residing in said first memory; a first arithmetic and logic unit (ALU) coupled to said first memory for executing said first instruction; means coupled to said first ALU for generating a first outgoing transmission packet containing said second instruction and a link field for storing said second link address; and (c) a second cell coupled to said first cell through said interconnection network, said second cell comprising: a second receive queue coupled to said interconnection network for receiving said first outgoing transmission packet; a second memory coupled to said second receive queue for storing said second memory packet, said second memory packet being selectively disposed in said second cell and including a third instruction, a second data element and a third link address, said third link address identifying a third memory packet and forming a portion of said linked list of memory packets specifying an order of execution; a second ALU coupled to said second memory for executing said second instruction stored in said first outgoing transmission packet; and means coupled to said second ALU for generating a second outgoing transmission packet containing said third instruction and said third link address.
Claim 3
Dependent Claim
15 words
The computer of claim 1 wherein said first input queue comprises a bidirectional shift register.
Claim 4
Dependent Claim
14 words
The computer of claim 1 wherein said interconnection network comprises a two-bus bidirectional ring.
Claim 5
Dependent Claim
14 words
The computer of claim 1 wherein said interconnection network comprises a four-bus bidirectional ring.
Claim 6
Dependent Claim
13 words
The computer of claim 1 wherein said interconnection network comprises a unidirectional Torus.
Claim 7
Dependent Claim
20 words
The computer of claim 1 further comprising a global synchronous clock coupled to said first cell and said second cell.
Claim 8
Dependent Claim
42 words
The computer of claim 6 further comprising a watchdog timer in said first cell, said timer generating a signal indicating that said first incoming receive queue has not changed state within a predetermined number of clock cycles of said global synchronous clock.
Claim 9
Dependent Claim
33 words
The computer of claim 1 wherein said interconnection network has a first width and said first incoming outgoing transmission packet has a second width, said first width being different from said second width.
Claim 10
Dependent Claim
15 words
The computer of claim 8 wherein said first width is less than said second width.
Claim 11
Dependent Claim
25 words
The computer of claim 9 wherein said interconnection network forwards a first incoming portion and a second portion of said first outgoing transmission packet serially.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |