System for modeling an integrated chip package and method of operation

Claim 3

The system of claim 1, wherein the parametric processor comprises: a parameter acquisition device operable to acquire said plurality of parameter values for said plurality of parameters based on said integrated chip package; and a storage device coupled to the parameter acquisition device and to the volume generator and operable to store the plurality of parameter values.

Claim 8

A computer system for finite element analysis of an integrated chip package, comprising: a parametric processor operable to acquire a plurality of parameter values for a plurality of parameters based on said integrated chip package, wherein the plurality of parameters define spacial relationships between a plurality of parts of the integrated chip package; a volume generator coupled to the parametric processor and operable to generate a plurality of volume coordinates for a plurality of volumes associated with the plurality of parts of the integrated chip package by using the plurality of parameter values; a mesh generator coupled to the volume generator and operable to subdivide the plurality of volumes into a plurality of elements; a finite element analysis processor coupled to the mesh generator and operable to analyze a model of an integrated chip package by calculating an effect of stress on the plurality of elements; a display coupled to the finite element analysis processor and operable to display a result from the finite element analysis processor, wherein the parametric processor comprises: a parameter acquisition device operable to acquire said plurality of parameter values for said plurality of parameters; and a storage device which is coupled to the parameter acquisition device and to the volume generator and is operable to store the plurality of parameter values, wherein the volume generator comprises: a symmetry offset generator coupled to the parametric processor and operable to generate a symmetry offset, wherein the symmetry offset is generated using a model symmetry type acquired as a parameter value; a volume coordinates generator coupled to the symmetry offset generator, comprising: a pin volume coordinates generator coupled to the symmetry offset generator and operable to generate said plurality of volume coordinates for said plurality of volumes associated with a plurality of pins of the integrated chip package using the plurality of parameter values; a component volume coordinates generator coupled to the pin volume coordinates generator and operable to generate said plurality of volume coordinates for said plurality of volumes associated with a plurality of components of the integrated chip package by using the plurality of parameter values; a volume coordinates tester coupled to the volume coordinates generator and operable to test the plurality of volume coordinates and to create a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; and a storage device coupled to the volume coordinates generator and operable to store the list of volume coordinates for passing volumes.

Claim 9

A computer system for finite element analysis of an integrated chip package, comprising: a parametric processor operable to acquire a plurality of parameter values for a plurality of parameters based on said integrated chip package, wherein the plurality of parameters define spacial relationships between a plurality of parts of the integrated chip package; a volume generator coupled to the parametric processor and operable to generate a plurality of volume coordinates for a plurality of volumes associated with the plurality of parts of the integrated chip package by using the plurality of parameter values; a mesh generator coupled to the volume generator and operable to subdivide the plurality of volumes into a plurality of elements; a finite element analysis processor coupled to the mesh generator and operable to analyze a model of an integrated chip package by calculating an effect of stress on the plurality of elements; a display coupled to the finite element analysis processor and operable to display a result from the finite element analysis processor, wherein the parametric processor comprises: a parameter acquisition device operable to acquire said plurality of parameter values for said plurality of parameters; and a storage device which is coupled to the parameter acquisition device and to the volume generator and is operable to store the plurality of parameter values, wherein the volume generator comprises: a symmetry offset generator coupled to the parametric processor and operable to generate a symmetry offset, wherein the symmetry offset is generated using a model symmetry type acquired as a parameter value; a volume coordinates generator coupled to the symmetry offset generator, comprising: a pin volume coordinates generator coupled to the symmetry offset generator and operable to generate said plurality of volume coordinates for said plurality of volumes associated with a plurality of pins of the integrated chip package using the plurality of parameter values; a component volume coordinates generator coupled to the pin volume coordinates generator and operable to generate said plurality of volume coordinates for said plurality of volumes associated with a plurality of components of the integrated chip package by using the plurality of parameter values; a volume coordinates tester coupled to the volume coordinates generator and operable to test the plurality of volume coordinates and to create a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; and a storage device coupled to the volume coordinates generator and operable to store the list of volume coordinates for passing volumes.

Claim 12

A computer system for finite element analysis of an integrated chip package, comprising: a parametric processor operable to acquire a plurality of parameter values for a plurality of parameters based on said integrated chip package and to obtain a symmetry offset based on said parameters, wherein the plurality of parameters define spacial relationships between a plurality of parts of the integrated chip package; and a volume generator coupled to the parametric processor and operable to generate a plurality of volume coordinates in accordance with said symmetry offset for a plurality of volumes associated with the plurality of parts of the integrated chip package by using the plurality of parameter values; a mesh generator coupled to the volume generator and operable to subdivide the plurality of volumes into a plurality of elements; a finite element analysis processor coupled to the mesh generator and operable to analyze a model of a integrated chip package by calculating an effect of stress on the plurality of elements; and a display coupled to the finite element analysis processor and operable to display a result from the finite element analysis processor.

Claim 13

A computer system for finite element analysis of an integrated chip package, comprising: a parametric processor operable to acquire a plurality of parameter values for a plurality of parameters based on said integrated chip package and to obtain a symmetry offset based on said parameters, wherein the plurality of parameters define spacial relationships between a plurality of parts of the integrated chip package; and a volume generator coupled to the parametric processor and operable to generate a plurality of volume coordinates in accordance with said symmetry offset for a plurality of volumes associated with the plurality of parts of the integrated chip package by using the plurality of parameter values; a mesh generator coupled to the volume generator and operable to subdivide the plurality of volumes into a plurality of elements; a finite element analysis processor coupled to the mesh generator and operable to analyze a model of a integrated chip package by calculating an effect of stress on the plurality of elements; and a display coupled to the finite element analysis processor and operable to display a result from the finite element analysis processor.

Claim 14

The computer system of claim 7, wherein the parametric processor comprises: a parameter acquisition device operable to acquire said plurality of parameter values for said plurality of parameters; and a storage device which is coupled to the parameter acquisition device and to the volume generator and is operable to store the plurality of parameter values.

Claim 15

A computer system for finite element analysis of an integrated chip package, comprising: a parametric processor operable to acquire a plurality of parameter values for a plurality of parameters based on said integrated chip package, wherein the plurality of parameters define spacial relationships between a plurality of parts of the integrated chip package; a volume generator coupled to the parametric processor and operable to generate a plurality of volume coordinates for a plurality of volumes associated with the plurality of parts of the integrated chip package by using the plurality of parameter values; a mesh generator coupled to the volume generator and operable to subdivide the plurality of volumes into a plurality of elements; and a finite element analysis processor coupled to the mesh generator and operable to analyze a model of an integrated chip package by calculating an effect of stress on the plurality of elements; a display coupled to the finite element analysis processor and operable to display a result from the finite element analysis processor, wherein the volume generator comprises: a symmetry offset generator coupled to the parametric processor and operable to generate a symmetry offset, wherein the symmetry offset is generated using a model symmetry type acquired as a parameter value; a volume coordinates generator coupled to the symmetry offset generator and operable to generate said plurality of volume coordinates for said plurality of volumes associated with a plurality of parts of the integrated chip package using the plurality of parameter values; a volume coordinates tester coupled to the volume coordinates generator and operable to test the plurality of volume coordinates and to create a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; and a storage device coupled to the volume coordinates generator and operable to store the list of volume coordinates for passing volumes.

Claim 16

A computer system for finite element analysis of an integrated chip package, comprising: a parametric processor operable to acquire a plurality of parameter values for a plurality of parameters based on said integrated chip package, wherein the plurality of parameters define spacial relationships between a plurality of parts of the integrated chip package; a volume generator coupled to the parametric processor and operable to generate a plurality of volume coordinates for a plurality of volumes associated with the plurality of parts of the integrated chip package by using the plurality of parameter values; a mesh generator coupled to the volume generator and operable to subdivide the plurality of volumes into a plurality of elements; and a finite element analysis processor coupled to the mesh generator and operable to analyze a model of an integrated chip package by calculating an effect of stress on the plurality of elements; a display coupled to the finite element analysis processor and operable to display a result from the finite element analysis processor, wherein the volume generator comprises: a symmetry offset generator coupled to the parametric processor and operable to generate a symmetry offset, wherein the symmetry offset is generated using a model symmetry type acquired as a parameter value; a volume coordinates generator coupled to the symmetry offset generator and operable to generate said plurality of volume coordinates for said plurality of volumes associated with a plurality of parts of the integrated chip package using the plurality of parameter values; a volume coordinates tester coupled to the volume coordinates generator and operable to test the plurality of volume coordinates and to create a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; and a storage device coupled to the volume coordinates generator and operable to store the list of volume coordinates for passing volumes.

Claim 17

A computer-implemented method for modeling an integrated chip package using a computer system, comprising the steps of: processing parameters to acquire a plurality of parameter values for a plurality of parameters, wherein the plurality of parameters defines spacial relationships between a plurality of parts of the integrated chip package; generating a symmetry offset, wherein the symmetry offset is generated using a model symmetry type acquired as a parameter value; generating a plurality of pin volume coordinates for a plurality of volumes associated with a plurality of pins of the integrated chip package using the plurality of parameter values; and generating a plurality of component volume coordinates for a plurality of volumes associated with a plurality of components of the integrated chip package by using the plurality of parameter values to model the integrated chip package.

Claim 18

A computer-implemented method for modeling an integrated chip package using a computer system, comprising the steps of: processing parameters to acquire a plurality of parameter values for a plurality of parameters, wherein the plurality of parameters defines spacial relationships between a plurality of parts of the integrated chip package; generating a symmetry offset, wherein the symmetry offset is generated using a model symmetry type acquired as a parameter value; generating a plurality of pin volume coordinates for a plurality of volumes associated with a plurality of pins of the integrated chip package using the plurality of parameter values; and generating a plurality of component volume coordinates for a plurality of volumes associated with a plurality of components of the integrated chip package by using the plurality of parameter values to model the integrated chip package.

Claim 19

The computer-implemented method of claim 10, wherein the step of generating a symmetry offset comprises the steps of: checking a model symmetry type acquired as a parameter value in the step of processing parameters; and generating a symmetry offset using the model symmetry type.

Claim 20

The computer-implemented method of claim 10, wherein the step of generating a plurality of pin volume coordinates comprises the steps of: creating a plurality of pin volume coordinates for a plurality of volumes associated with a plurality of pins on a first side of a first axis of the integrated chip package, wherein a number of the plurality of pins is specified by one of the plurality of parameter values; creating a plurality of pin volume coordinates for a plurality of volumes associated with a plurality of pins on a second side of a first axis of the integrated chip package, wherein a number of the plurality of pins is specified by one of the plurality of parameter values; creating a plurality of pin volume coordinates for a plurality of volumes associated with a plurality of pins on a first side of a second axis of the integrated chip package, wherein a number of the plurality of pins is specified by one of the plurality of parameter values acquired from the user of the computer system; and creating a plurality of pin volume coordinates for a plurality of volumes associated with a plurality of pins on a second side of a second axis of the integrated chip package, wherein a number of the plurality of pins is specified by one of the plurality of parameter values.

Claim 21

The computer-implemented method of claim 12, wherein the steps of creating a plurality of pin volume coordinates comprise the steps of: calculating a plurality of volume coordinates for a first volume associated with a bottom-most pin of a side of the integrated chip package; testing the plurality of volume coordinates for the first volume and maintaining a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; repeating the steps of calculating and testing until a plurality of volume coordinates have been calculated for all volumes associated with the bottom-most pin; recalculating a plurality of volume coordinates for a second volume associated with a next pin of the side of the integrated chip package if the side of the integrated chip package has more than one pin, wherein the step of recalculating is performed by incrementing the plurality of volume coordinates for the second volume associated with the bottom-most pin by one pin pitch dimension and wherein the pin pitch dimension is a parameter value; testing the plurality of volume coordinates for the second volume and maintaining the list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; repeating the steps of recalculating and testing until a plurality of volume coordinates have been calculated for all volumes within all pins on the side of the integrated chip package.

Claim 22

The computer-implemented method of claim 13, wherein the step of testing the plurality of volume coordinates for the first volume or the second volume comprises the steps of: testing a plurality of volume coordinates for a volume by subtracting the symmetry offset from the plurality of volume coordinates; setting every negative ordinate of the plurality of volume coordinates equal to zero; and adding the volume to a list of volume coordinates for passing volumes if the volume has a thickness in all directions greater than zero.

Claim 23

The computer-implemented method of claim 10, wherein the step of generating a plurality of component volume coordinates comprises the steps of: creating a first plurality of volume coordinates for a plurality of volumes associated with a printed wiring board; testing each of the first plurality of volume coordinates after each of the first plurality of volume coordinates is created and maintaining a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; creating a second plurality of volume coordinates for a plurality of volumes associated with a chip; testing each of the second plurality of volume coordinates after each of the second plurality of volume coordinates is created and maintaining a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; creating a third plurality of volume coordinates for a plurality of volumes associated with a die attach; testing each of the third plurality of volume coordinates after each of the third plurality of volume coordinates is created and maintaining a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; creating a fourth plurality of volume coordinates for a plurality of volumes associated with a pad; testing each of the fourth plurality of volume coordinates after each of the fourth plurality of volume coordinates is created and maintaining a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; creating a fifth plurality of volume coordinates for a plurality of volumes associated with a plurality of tie straps; testing each of the fifth plurality of volume coordinates after each of the fifth plurality of volume coordinates is created and maintaining a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type; creating a sixth plurality of volume coordinates for a plurality of volumes associated with a mold compound; and testing each of the sixth plurality of volume coordinates after each of the sixth plurality of volume coordinates is created and maintaining a list of volume coordinates for passing volumes, wherein a volume is a passing volume if the volume is included within a portion of the integrated chip package to be modeled with the model symmetry type.

Claim 24

The computer-implemented method of claim 15, wherein the steps of testing comprise the steps of: testing a plurality of volume coordinates for a volume by subtracting the symmetry offset from the plurality of volume coordinates; setting every negative ordinate of the plurality of volume coordinates equal to zero; and adding the volume to a list of volume coordinates for passing volumes if the volume has a thickness in all directions greater than zero.