Impedance emulator

Claim 2

A bus terminator for terminating a conductor of a bus having an impedance associated therewith comprising: a voltage regulator providing a regulated voltage; an emulating FET having a first electrode, a second electrode, and a third electrode, said second and third electrodes adapted for being coupled in series between said voltage regulator and said conductor; and a control circuit coupled to said first electrode of said emulating FET for maintaining said emulating FET in a linear region of operation so as to provide a substantially fixed resistive impedance to said conductor, said substantially fixed resistive impedance substantially matching said impedance of said conductor.

Claim 3

The terminator recited in claim 1 wherein said emulating FET is an NMOS device and wherein said first electrode is a gate electrode, said second electrode is a drain electrode coupled to said voltage regulator, and said third electrode is a source electrode adapted for coupling to said conductor.

Claim 4

The terminator recited in claim 2 wherein said gate electrode of said NMOS device comprises a gate region and a gate contact, said source electrode of said NMOS device comprises a source regions and a source contact and said drain electrode of said NMOS device comprises a drain region and a drain contact and wherein said source region is centrally located and surrounded by a substantially annular gate region and a :substantially annular drain region.

Claim 5

The terminator recited in claim 1 further comprising a plurality of emulating FETs, each one adapted for coupling in series between said voltage regulator and said conductor and wherein said control circuit is coupled to said first electrode of a selected one of said plurality of emulating FETs.

Claim 6

A bus terminator for terminating a conductor of a bus having an impedance associated therewith comprising: a voltage regulator providing a regulated voltage; an emulating FET having a first electrode, a second electrode, and a third electrode, said second and third electrodes adapted for being coupled in series between said voltage regulator and said conductor; and a control circuit coupled to said first electrode of said emulating FET for maintaining said emulating FET in a linear region of operation so as to provide a resistive impedance to said conductor, said resistive impedance substantially matching said impedance of said conductor, said control circuit comprising: (a) a control FET having a gate electrode, a source electrode, and a drain electrode; (b) a variable resistor having an adjustable resistance value associated therewith and coupled in series with said control FET; and (c) an amplifier providing an output signal coupled to said gate electrode of a control FET and said gate electrode of said emulating FET, said output signal causing said control FET and said emulating FET to provide an impedance having a predetermined relationship with respect to said resistance value of said resistor.

Claim 7

A bus terminator for terminating a conductor of a bus having an impedance associated therewith comprising: a voltage regulator providing a regulated voltage; an emulating FET having a first electrode, a second electrode, and a third electrode, said second and third electrodes adapted for being coupled in series between said voltage regulator and said conductor; and a control circuit coupled to said first electrode of said emulating FET for maintaining said emulating FET in a linear region of operation so as to provide a resistive impedance to said conductor, said resistive impedance substantially matching said impedance of said conductor, said control circuit comprising: (a) a control FET having a gate electrode, a source electrode, and a drain electrode; (b) a variable resistor having an adjustable resistance value associated therewith and coupled in series with said control FET; and (c) an amplifier providing an output signal coupled to said gate electrode of a control FET and said gate electrode of said emulating FET, said output signal causing said control FET and said emulating FET to provide an impedance having a predetermined relationship with respect to said resistance value of said resistor.

Claim 8

The terminator recited in claim 5 wherein said resistor is a variable resistor having a variable resistance value associated therewith so that said impedance provided by said emulating FET is adjustable in accordance with said variable resistance value.

Claim 9

The terminator recited in claim 5 wherein said amplifier has a pair of inputs, a first one receiving a reference voltage of approximately one-half the regulated voltage and a second one coupled to said resistor and said source electrode of said control FET.

Claim 10

The terminator recited in claim 5 wherein said amplifier includes a temperature compensation circuit for compensating for the effect of temperature variations on said resistance value of said resistor.

Claim 11

A circuit for providing an emulated impedance for terminating a conductor having an impedance associated therewith comprising: a voltage source; an emulating FET coupled to said voltage source and having a gate electrode, a source electrode, and a drain electrode, wherein said emulating FET has said emulated impedance between said drain and source electrodes, said emulated impedance substantially matching said impedance of said conductor; and a control circuit coupled to said gate electrode of said emulating FET for providing a control signal to maintain said emulating FET in a linear region of operation, said control circuit comprising a variable resistor having an adjustable resistance value, wherein said control signal causes said emulating FET to provide an impedance proportional to said resistance value and adjustable in accordance with said variable resistance value, said emulated impedance between said drain and source electrodes being substantially fixed at said impedance proportional to said resistance value.

Claim 12

A circuit for providing an emulated impedance for terminating a conductor having an impedance associated therewith comprising: a voltage source; an emulating FET coupled to said voltage source and having a gate electrode, a source electrode, and a drain electrode, wherein said emulating FET has said emulated impedance between said drain and source electrodes, said emulated impedance substantially matching said impedance of said conductor; and a control circuit coupled to said gate electrode of said emulating FET for providing a control signal to maintain said emulating FET in a linear region of operation, said control circuit comprising a variable resistor having an adjustable resistance value, wherein said control signal causes said emulating FET to provide an impedance proportional to said resistance value and adjustable in accordance with said variable resistance value, said emulated impedance between said drain and source electrodes being substantially fixed at said impedance proportional to said resistance value.

Claim 13

The circuit recited in claim 9 wherein said control circuit further comprises a control FET having a gate electrode, a source electrode, and a drain electrode and an amplifier providing an output signal coupled to said gate electrode of said control FET and said gate electrode of said emulating FET.

Claim 14

The circuit recited in claim 9 wherein said amplifier has a pair of inputs, a first one receiving a reference voltage equal to a predetermined fraction of a voltage provided by said voltage source and a second one coupled to said resistor and said control FET.

Claim 15

The circuit recited in claim 9 wherein said emulating FET is an NMOS device.

Claim 16

The circuit recited in claim 9 wherein said emulating FET is an NMOS device comprising a source region, a substantially annular shaped gate region disposed around said source region, and a substantially annular drain region disposed around said gate region.

Claim 17

A terminator for terminating a conductor having an impedance associated therewith comprising: a voltage source having a voltage level associated therewith; a plurality of emulating FETs, each having a first electrode, a second electrode, and a third electrode, said second and third electrodes of each of said plurality of emulating FETs adapted for being coupled in series between said voltage source and said conductor; and a control circuit coupled to said first electrode of a selected one of said plurality of emulating FETs for maintaining said selected emulating FET in a linear region of operation so as to provide a substantially fixed impedance to said conductor corresponding to said selected emulating FET, said substantially fixed impedance substantially matching said impedance of said conductor.

Claim 18

A terminator for terminating a conductor having an impedance associated therewith comprising: a voltage source having a voltage level associated therewith; a plurality of emulating FETs, each having a first electrode, a second electrode, and a third electrode, said second and third electrodes of each of said plurality of emulating FETs adapted for being coupled in series between said voltage source and said conductor; and a control circuit coupled to said first electrode of a selected one of said plurality of emulating FETs for maintaining said selected emulating FET in a linear region of operation so as to provide a substantially fixed impedance to said conductor corresponding to said selected emulating FET, said substantially fixed impedance substantially matching said impedance of said conductor.

Claim 19

The terminator recited in claim 14 further comprising a disconnect switch for selectively disconnecting ones of said plurality of emulating FETs from said conductor.

Claim 20

The terminator recited in claim 15 wherein said disconnect switch is responsive to a common control signal for selecting one of said plurality of emulating FETs for connection to said conductor or disconnecting each of said plurality of emulating FETs from said conductor.

Claim 21

The terminator according to claim 14, wherein said control circuit further comprises an amplifier arid a control FET coupled in a feedback relationship to said amplifier.

Claim 22

The terminator according to claim 17, wherein said control FET includes a gate electrode, a source electrode, and a drain electrode and, said amplifier includes a pair of inputs and an output, wherein said amplifier output is coupled to said first electrode of a selected one of said plurality of emulating FETs and to said control FET gate electrode and said control FET source electrode is coupled to a first of said pair of inputs and said control FET drain electrode is coupled to said voltage source.

Claim 23

The terminator according to claim 16, further comprising a disconnect/impedance selection circuit coupled to said disconnect switch and responsive to said common control signal having an impedance and a logic state.

Claim 24

The terminator according to claim 19, wherein said disconnect/impedance circuit is responsive to said impedance and said logic state of said common control signal for selecting one of said plurality of emulating FETs for connection to said conductor or disconnecting each of said plurality of emulating FETs from said conductor.

Claim 25

A terminator for terminating a conductor having an impedance associated therewith comprising: a voltage source having a voltage level associated therewith; an emulating FET having a gate electrode, a source electrode, and a drain electrode, said source and drain electrodes adapted for being coupled in series between said voltage source and said conductor; a control circuit for maintaining said emulating FET in a linear region of operation so as to provide a substantially fixed impedance of said conductor, said substantially fixed impedance substantially matching said impedance of said conductor; and a disconnected switch coupled to said gate electrode of said emulating FET for turning off said emulating FET in response to a disconnect signal provided to said terminator.

Claim 26

A terminator for terminating a conductor having an impedance associated therewith comprising: a voltage source having a voltage level associated therewith; an emulating FET having a gate electrode, a source electrode, and a drain electrode, said source and drain electrodes adapted for being coupled in series between said voltage source and said conductor; a control circuit for maintaining said emulating FET in a linear region of operation so as to provide a substantially fixed impedance of said conductor, said substantially fixed impedance substantially matching said impedance of said conductor; and a disconnected switch coupled to said gate electrode of said emulating FET for turning off said emulating FET in response to a disconnect signal provided to said terminator.

Claim 27

The terminator recited in claim 21 wherein said disconnect switch comprises a first switch connected between said gate electrode of said emulating FET and ground and a second switch connected between said gate electrode of said emulating FET and said control circuit.

Claim 28

The terminator according to claim 21, wherein said control circuit further comprises an amplifier and a control FET coupled in a feedback relationship to said amplifier, said amplifier coupled to said emulating FET gate electrode.

Claim 29

The terminator according to claim 23, wherein said control FET includes a first electrode, a second electrode, and a third electrode and, said amplifier includes a pair of inputs and an output, wherein said amplifier output is coupled to said gate electrode of a selected one of said plurality of emulating FETs and to said control FET first electrode and said control FET second electrode is coupled to a first of said pair of inputs and said control FET third electrode is coupled to said voltage source.

Claim 30

A terminator for terminating a conductor comprising: a voltage source having a voltage level associated therewith; an emulating FET having a gate electrode, a source electrode, and a drain electrode, said source and drain electrodes adapted for being coupled in series between said voltage source and said conductor; a control circuit for maintaining said emulating FET in a linear region of operation so as to provide a termination impedance to said conductor; and a disconnect switch coupled to said gate electrode of said emulating FET for turning off said emulating FET in response to a disconnect signal provided to said terminator; wherein said voltage source is responsive to said disconnect signal for entering a low power mode of operation.

Claim 31

A terminator for terminating a conductor comprising: a voltage source having a voltage level associated therewith; an emulating FET having a gate electrode, a source electrode, and a drain electrode, said source and drain electrodes adapted for being coupled in series between said voltage source and said conductor; a control circuit for maintaining said emulating FET in a linear region of operation so as to provide a termination impedance to said conductor; and a disconnect switch coupled to said gate electrode of said emulating FET for turning off said emulating FET in response to a disconnect signal provided to said terminator; wherein said voltage source is responsive to said disconnect signal for entering a low power mode of operation.

Claim 32

A circuit for terminating a conductor, said circuit comprising: (a) a voltage regulator providing a regulated voltage; (b) a first emulating FET having a gate electrode, a source electrode, and a drain electrode, said drain and source electrodes being adapted for coupling in series between said voltage regulator and said conductor; (c) a second emulating FET having a gate electrode, a source electrode, and a drain electrode, said drain and source electrodes adapted for coupling in series between said voltage regulator and said conductor; (d) a control circuit providing a control signal to maintain a selected one of said first and second emulating FETs in a linear region of operation, said control circuit comprising: (i) a control FET having a gate electrode, a source electrode, and a drain electrode coupled to said voltage regulator; (ii) a resistor coupled to said control FET; and (iii) an amplifier having a pair of input terminals and an output terminal, a first one of said pair of input terminals receiving a reference voltage, a second one of said pair of input terminals being coupled to said resistor, and said output terminal being coupled to said gate electrode said control FET; (e) a first switch network connected between said output of said amplifier and said gate electrode of said first emulating FET, said first switch network adapted for connecting said gate electrode of said first emulating FET to ground or to said output of said amplifier in response to a first switch control signal; (f) a second switch network connected between said output of said amplifier and said gate electrode of said second emulating FET, said second switch network adapted for connecting said gate electrode of said second emulating FET to ground or to said output of said amplifier in response to a second switch control signal; and (g) a disconnect/impedance selection circuit for generating said first and second switch control signals in response to a single user provided signal.

Claim 33

A circuit for terminating a conductor, said circuit comprising: (a) a voltage regulator providing a regulated voltage; (b) a first emulating FET having a gate electrode, a source electrode, and a drain electrode, said drain and source electrodes being adapted for coupling in series between said voltage regulator and said conductor; (c) a second emulating FET having a gate electrode, a source electrode, and a drain electrode, said drain and source electrodes adapted for coupling in series between said voltage regulator and said conductor; (d) a control circuit providing a control signal to maintain a selected one of said first and second emulating FETs in a linear region of operation, said control circuit comprising: (i) a control FET having a gate electrode, a source electrode, and a drain electrode coupled to said voltage regulator; (ii) a resistor coupled to said control FET; and (iii) an amplifier having a pair of input terminals and an output terminal, a first one of said pair of input terminals receiving a reference voltage, a second one of said pair of input terminals being coupled to said resistor, and said output terminal being coupled to said gate electrode said control FET; (e) a first switch network connected between said output of said amplifier and said gate electrode of said first emulating FET, said first switch network adapted for connecting said gate electrode of said first emulating FET to ground or to said output of said amplifier in response to a first switch control signal; (f) a second switch network connected between said output of said amplifier and said gate electrode of said second emulating FET, said second switch network adapted for connecting said gate electrode of said second emulating FET to ground or to said output of said amplifier in response to a second switch control signal; and (g) a disconnect/impedance selection circuit for generating said first and second switch control signals in response to a single user provided signal.

Claim 34

The circuit recited in claim 26 wherein said resistor of said control circuit is a thin film resistor.

Claim 35

The circuit recited in claim 26 further comprising a temperature compensation circuit for reducing the effect of temperature on said resistor of said control circuit.

Claim 36

A terminator for terminating a conductor having an impedance associated therewith comprising: a voltage source providing a reference voltage and a supply voltage; a plurality of emulating FETs, each having a first electrode, a second electrode, and a third electrode, said second and third electrodes of each of said plurality of emulating FETs adapted for being coupled in series between said reference voltage and said conductor, said plurality of emulating FETs each having a predetermined impedance; a control circuit including an amplifier and a control FET coupled in a feedback relationship to said amplifier, said amplifier coupled to said first electrode of a selected one of said plurality of emulating FETs for maintaining said selected emulating FET in a linear region of operation to present said predetermined impedance to said conductor corresponding to said selected emulating FET, said predetermined impedance substantially matching said impedance of said conductor; a disconnect switch for selectively disconnecting said plurality of emulating FETs from said conductor; and a disconnect/impedance selection circuit adapted for being coupled to said disconnect switch and responsive to a said single user provided signal controlling said disconnect/impedance selection circuit, wherein a first one of said plurality of emulating FETs is active presenting a first predetermined impedance to said conductor when said single user provided signal is in a first logic state having a first control impedance, and a second one of said plurality of emulating FETs is active presenting a second predetermined impedance to said conductor when said single user provided signal is in said first logic state having a second control impedance, and wherein said first and second ones of said plurality of emulating FETs are disconnected from said conductor when said single user provided signal is in a second logic state.

Claim 37

A terminator for terminating a conductor having an impedance associated therewith comprising: a voltage source providing a reference voltage and a supply voltage; a plurality of emulating FETs, each having a first electrode, a second electrode, and a third electrode, said second and third electrodes of each of said plurality of emulating FETs adapted for being coupled in series between said reference voltage and said conductor, said plurality of emulating FETs each having a predetermined impedance; a control circuit including an amplifier and a control FET coupled in a feedback relationship to said amplifier, said amplifier coupled to said first electrode of a selected one of said plurality of emulating FETs for maintaining said selected emulating FET in a linear region of operation to present said predetermined impedance to said conductor corresponding to said selected emulating FET, said predetermined impedance substantially matching said impedance of said conductor; a disconnect switch for selectively disconnecting said plurality of emulating FETs from said conductor; and a disconnect/impedance selection circuit adapted for being coupled to said disconnect switch and responsive to a said single user provided signal controlling said disconnect/impedance selection circuit, wherein a first one of said plurality of emulating FETs is active presenting a first predetermined impedance to said conductor when said single user provided signal is in a first logic state having a first control impedance, and a second one of said plurality of emulating FETs is active presenting a second predetermined impedance to said conductor when said single user provided signal is in said first logic state having a second control impedance, and wherein said first and second ones of said plurality of emulating FETs are disconnected from said conductor when said single user provided signal is in a second logic state.

Claim 38

The terminator according to claim 29, wherein said disconnect/impedance selection circuit comprises: (a) a current mirror; (b) a first and second comparator circuit coupled to said current mirror; (c) a disconnect logic circuit coupled to said first and second comparator circuit for providing a first and second switch control signal; and (d) an amplifier feedback circuit adapted for being coupled in series between said current mirror and said user provided control signal.

Claim 39

The terminator according to claim 30, wherein said current mirror comprises: first, second, and third current mirror FETs, each including a gate electrode, a source electrode, and a drain electrode, said first current mirror FET being diode connected; said first, second and third current mirror FET gate electrodes being commonly connected; said first, second, and third current mirror FET source electrodes being coupled to said supply voltage; said first current mirror FET drain electrode coupled to said amplifier feedback circuit, said second current mirror FET drain electrode coupled to said first comparator circuit, said third current mirror FET drain electrode coupled to said second comparator circuit.

Claim 40

The terminator according to claim 30, wherein said amplifier circuit comprises: a resistor having a first terminal and a second terminal, said first terminal receiving said user provided signal; an amplifier having a pair of input terminals and an output terminal, a first of said pair of input terminals coupled to said resistor second terminal, a second of said pair of input terminals receiving a threshold voltage; and an amplifier FET having a gate electrode, a source electrode, and a drain electrode, said gate electrode coupled to said amplifier output terminal, said drain electrode coupled to said current mirror, and said source electrode coupled to said resistor second terminal.

Claim 41

The terminator according to claim 30, wherein said first comparator circuit comprises: a first current source; and a first comparator having a pair of input terminals and an output terminal, a first of said pair of input terminals coupled to said current mirror and to said first current source, said output terminal coupled to said disconnect logic circuit, and a second of said pair of input terminals coupled to a comparator threshold voltage; said second comparator circuit comprising: a second current source; and a second comparator having a pair of input terminals and an output terminal, a first of said pair of input terminals coupled to said current mirror and to said second current source, said output terminal coupled to said disconnect logic circuit, and a second of said pair of input terminals coupled to said comparator threshold voltage.