US5589783A
Expired / Lapsed
US
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Variable input threshold adjustment
Assignee: STMicroelectronics lnc USA
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Filing: 1994-07-29
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Granted: 1996-12-31
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Expires: 2014-07-29
Abstract
Abstract According to the present invention, an integrated circuit device is capable of responding to more than one input threshold voltage level by making only minimal changes to the device. The input buffer of the integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means. Such control means include a bond option, a mask option, a fuse option, a register option, and a voltage detector option.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585; H03K19/0021; H03K19/0027
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
422 words
An integrated circuit device having a variable trip point adjustment, comprising: a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and a control input signal to the programmable input buffer, wherein when the control input signal is equal to a first logic level, a first trip point of the integrated circuit device is defined, and when the control input signal is equal to a second logic level, a second trip point of the integrated circuit device is defined, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level, wherein the programmable input buffer is comprised of a bond pad, a logic gate, a first transistor having a first source/drain, a second source/drain, and a gate, a second transistor having a first source/drain, a second source/drain, and a gate, a third transistor having a first source/drain, a second source/drain, and a gate, a fourth transistor having a first source/drain, a second source/drain, and a gate, a fifth transistor having a first source/drain, a second source/drain, and a gate, and a sixth transistor having a first source/drain, a second source/drain, and a gate; and wherein the chip enable signal controls the gate of the first transistor and the gate of the sixth transistor; wherein a bond pad signal generated by the bond pad controls the gate of the second transistor, the gate of the third transistor, and the gate of the fifth transistor; wherein the chip enable signal is a first input signal to the logic gate, the control input signal is a second input signal to the logic gate, and the logic gate generates a derivative chip enable signal which controls the gate of the fourth transistor; and wherein the first source/drain of the first transistor and the first source/drain of the fourth transistor are connected to a first supply voltage; the second source/drain of the third transistor and the second source/drain of the sixth transistor are connected to a second supply voltage; the second source/drain of the first transistor is connected to the first source/drain of the second transistor; the second source/drain of the second transistor, the first source/drain of the third transistor, the second source/drain of the fifth transistor, and the first source/drain of the sixth transistor are connected together to form an output signal; and the second source/drain of the fourth transistor is connected to the first source/drain of the fifth transistor.
Claim 2
Dependent Claim
422 words
An integrated circuit device having a variable trip point adjustment, comprising: a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and a control input signal to the programmable input buffer, wherein when the control input signal is equal to a first logic level, a first trip point of the integrated circuit device is defined, and when the control input signal is equal to a second logic level, a second trip point of the integrated circuit device is defined, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level, wherein the programmable input buffer is comprised of a bond pad, a logic gate, a first transistor having a first source/drain, a second source/drain, and a gate, a second transistor having a first source/drain, a second source/drain, and a gate, a third transistor having a first source/drain, a second source/drain, and a gate, a fourth transistor having a first source/drain, a second source/drain, and a gate, a fifth transistor having a first source/drain, a second source/drain, and a gate, and a sixth transistor having a first source/drain, a second source/drain, and a gate; and wherein the chip enable signal controls the gate of the first transistor and the gate of the sixth transistor; wherein a bond pad signal generated by the bond pad controls the gate of the second transistor, the gate of the third transistor, and the gate of the fifth transistor; wherein the chip enable signal is a first input signal to the logic gate, the control input signal is a second input signal to the logic gate, and the logic gate generates a derivative chip enable signal which controls the gate of the fourth transistor; and wherein the first source/drain of the first transistor and the first source/drain of the fourth transistor are connected to a first supply voltage; the second source/drain of the third transistor and the second source/drain of the sixth transistor are connected to a second supply voltage; the second source/drain of the first transistor is connected to the first source/drain of the second transistor; the second source/drain of the second transistor, the first source/drain of the third transistor, the second source/drain of the fifth transistor, and the first source/drain of the sixth transistor are connected together to form an output signal; and the second source/drain of the fourth transistor is connected to the first source/drain of the fifth transistor.
Claim 3
Independent Claim
460 words
A method for variable trip point adjustment of an integrated circuit device, comprising the steps of: detecting a logic level of a control input signal to a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and adjusting a trip point of the programmable input buffer of the integrated circuit device based upon the logic level of the input control signal, wherein when the control input signal is equal to a first logic level, the trip point of the integrated circuit device is adjusted to a first trip point, and when the control input signal is equal to a second logic level, the trip point of the integrated circuit device is adjusted to a second trip point, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level, wherein the programmable input buffer is comprised of a bond pad, a logic gate, a first transistor having a first source/drain, a second source/drain, and a gate, a second transistor having a first source/drain, a second source/drain, and a gate, a third transistor having a first source/drain, a second source/drain, and a gate, a fourth transistor having a first source/drain, a second source/drain, and a gate, a fifth transistor having a first source/drain, a second source/drain, and a gate, and a sixth transistor having a first source/drain, a second source/drain, and a gate; and wherein the chip enable signal controls the gate of the first transistor and the gate of the sixth transistor; wherein a bond pad signal generated by the bond pad controls the gate of the second transistor, the gate of the third transistor, and the gate of the fifth transistor; wherein the chip enable signal is a first input signal to the logic gate, the control input signal is a second input signal to the logic gate, and the logic gate generates a derivative chip enable signal which controls the gate of the fourth transistor; and wherein the first source/drain of the first transistor and the first source/drain of the fourth transistor are connected to a first supply voltage; the second source/drain of the third transistor and the second source/drain of the sixth transistor are connected to a second supply voltage; the second source/drain of the first transistor is connected to the first source/drain of the second transistor; the second source/drain of the second transistor, the first source/drain of the third transistor, the second source/drain of the fifth transistor, and the first source/drain of the sixth transistor are connected together to form an output signal; and the second source/drain of the fourth transistor is connected to the first source/drain of the fifth transistor.
Claim 4
Independent Claim
460 words
A method for variable trip point adjustment of an integrated circuit device, comprising the steps of: detecting a logic level of a control input signal to a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and adjusting a trip point of the programmable input buffer of the integrated circuit device based upon the logic level of the input control signal, wherein when the control input signal is equal to a first logic level, the trip point of the integrated circuit device is adjusted to a first trip point, and when the control input signal is equal to a second logic level, the trip point of the integrated circuit device is adjusted to a second trip point, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level, wherein the programmable input buffer is comprised of a bond pad, a logic gate, a first transistor having a first source/drain, a second source/drain, and a gate, a second transistor having a first source/drain, a second source/drain, and a gate, a third transistor having a first source/drain, a second source/drain, and a gate, a fourth transistor having a first source/drain, a second source/drain, and a gate, a fifth transistor having a first source/drain, a second source/drain, and a gate, and a sixth transistor having a first source/drain, a second source/drain, and a gate; and wherein the chip enable signal controls the gate of the first transistor and the gate of the sixth transistor; wherein a bond pad signal generated by the bond pad controls the gate of the second transistor, the gate of the third transistor, and the gate of the fifth transistor; wherein the chip enable signal is a first input signal to the logic gate, the control input signal is a second input signal to the logic gate, and the logic gate generates a derivative chip enable signal which controls the gate of the fourth transistor; and wherein the first source/drain of the first transistor and the first source/drain of the fourth transistor are connected to a first supply voltage; the second source/drain of the third transistor and the second source/drain of the sixth transistor are connected to a second supply voltage; the second source/drain of the first transistor is connected to the first source/drain of the second transistor; the second source/drain of the second transistor, the first source/drain of the third transistor, the second source/drain of the fifth transistor, and the first source/drain of the sixth transistor are connected together to form an output signal; and the second source/drain of the fourth transistor is connected to the first source/drain of the fifth transistor.
Claim 5
Independent Claim
154 words
A method for variable trip point adjustment of an integrated circuit device, comprising the steps of: detecting a logic level of a control input signal to a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and adjusting a trip point of the programmable input buffer of the integrated circuit device based upon the logic level of the input control signal, wherein when the control input signal is equal to a first logic level, the trip point of the integrated circuit device is adjusted to a first trip point, and when the control input signal is equal to a second logic level, the trip point of the integrated circuit device is adjusted to a second trip point, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level.
Claim 6
Independent Claim
154 words
A method for variable trip point adjustment of an integrated circuit device, comprising the steps of: detecting a logic level of a control input signal to a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and adjusting a trip point of the programmable input buffer of the integrated circuit device based upon the logic level of the input control signal, wherein when the control input signal is equal to a first logic level, the trip point of the integrated circuit device is adjusted to a first trip point, and when the control input signal is equal to a second logic level, the trip point of the integrated circuit device is adjusted to a second trip point, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level.
Claim 7
Dependent Claim
29 words
The method of claim 3, wherein the first trip point is compatible with a 5 volt standard and the second trip point is compatible with a 3.3 volt standard.
Claim 8
Dependent Claim
33 words
The method of claim 3, wherein the first trip point is compatible with a TTL (Transistor-Transistor Logic) standard and the second trip point is compatible with a CMOS (Complementary Metal Oxide Semiconductor) standard.
Claim 9
Dependent Claim
116 words
An integrated circuit device having a variable trip point adjustment, comprising: a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and a control input signal to the programmable input buffer, wherein when the control input signal is equal to a first logic level, a first trip point of the integrated circuit device is defined, and when the control input signal is equal to a second logic level, a second trip point of the integrated circuit device is defined, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level.
Claim 10
Dependent Claim
116 words
An integrated circuit device having a variable trip point adjustment, comprising: a programmable input buffer of an integrated circuit device, wherein the integrated circuit device has a supply voltage; and a control input signal to the programmable input buffer, wherein when the control input signal is equal to a first logic level, a first trip point of the integrated circuit device is defined, and when the control input signal is equal to a second logic level, a second trip point of the integrated circuit device is defined, wherein a chip enable signal of the integrated circuit device may determine whether the control input signal is equal to the first logic level or the second logic level.
Claim 11
Dependent Claim
29 words
The device of claim 6, wherein the first trip point is compatible with a 5 volt standard and the second trip point is compatible with a 3.3 volt standard.
Claim 12
Dependent Claim
33 words
The device of claim 6, wherein the first trip point is compatible with a TTL (Transistor-Transistor Logic) standard and the second trip point is compatible with a CMOS (Complementary Metal Oxide Semiconductor) standard.
Claim 13
Dependent Claim
28 words
The device of claim 6, wherein the programmable input buffer is connected to a bond pad which is connected to a device pin of the integrated circuit device.
Claim 14
Dependent Claim
16 words
The device of claim 6, wherein the input control signal is generated by a control means.
Claim 15
Dependent Claim
13 words
The device of claim 10, wherein the control means is a bond option.
Claim 16
Dependent Claim
13 words
The device of claim 10, wherein the control means is a mask option.
Claim 17
Dependent Claim
15 words
The device of claim 12, wherein the control means is a polycrystalline silicon mask option.
Claim 18
Dependent Claim
14 words
The device of claim 12, wherein the control means is a metal mask option.
Claim 19
Dependent Claim
35 words
The device of claim 10, wherein the control means is a fuse option having a fuse element and when the fuse element is blown, the input control signal is equal to the first logic level.
Claim 20
Dependent Claim
34 words
The device of claim 10, wherein the control means is controlled by a register circuit having a register element and the state of the register element controls the state of the input control signal.
Claim 21
Dependent Claim
68 words
The device of claim 10, wherein the control means is controlled by a voltage detector which detects the supply voltage of the integrated circuit device, and wherein when the supply voltage is above a predetermined level, the control input signal is equal to the first logic state, and when the supply voltage is below the predetermined level, the control input signal is equal to the second logic state.
Claim 22
Dependent Claim
13 words
The device of claim 6, wherein the integrated circuit device is a memory.
Claim 23
Dependent Claim
14 words
The device of claim 6, wherein the integrated circuit device is a logic device.
Claim 24
Dependent Claim
15 words
The device of claim 19, wherein the logic device is a Programmable Logic Device (PLD).
Claim 25
Dependent Claim
13 words
The device of claim 6, wherein the integrated circuit device is a processor.
Claim 26
Dependent Claim
11 words
The device of claim 21, wherein the processor is a microprocessor.
Claim 27
Dependent Claim
15 words
The device of claim 6, wherein the integrated circuit device is a gate array device.
Claim 28
Dependent Claim
17 words
The device of claim 23, wherein the gate array device is an Application Specific Integrated Circuit (ASIC).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |