Patent US5590358A successfully refreshed from Google Patents.
US5590358A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor with word-aligned branch target in a byte-oriented instruction set
Assignee: FGP CORP
•
Filing: 1994-09-16
•
Granted: 1996-12-31
•
Expires: 2014-09-16
Abstract
Abstract A microcontroller or processor architecture that performs word aligned multi-byte fetches but allows byte aligned instructions. Jump target addresses are word aligned, resulting in a word aligned fetch of the jump-to instruction. An assembler or compiler loads code into an instruction memory with branch instruction target addresses aligned on word boundaries. Returns from interrupts load the program counter with a complete return address which is byte aligned.
Inventors
- 👤 Ori K. Mizrahi-Shalom
- 👤 Kung-Ling Ko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3816; G06F9/30145; G06F9/30149; G06F9/32; G06F9/321; G06F9/322; G06F9/323; G06F9/324; G06F9/3804; G06F9/3806
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
74 words
A system, comprising: instruction means for aligning scheduled program flow change targets on word boundaries; and a processor, comprising: variable means for fetching variable size instructions alignable on byte boundaries and aligning the instructions for execution; flow change means for fetching the instructions at the flow change targets using a word boundary address; execution means for executing the fetched instructions; and transfer means for returning from unplanned program flow changes using byte aligned addresses.
Claim 2
Independent Claim
74 words
A system, comprising: instruction means for aligning scheduled program flow change targets on word boundaries; and a processor, comprising: variable means for fetching variable size instructions alignable on byte boundaries and aligning the instructions for execution; flow change means for fetching the instructions at the flow change targets using a word boundary address; execution means for executing the fetched instructions; and transfer means for returning from unplanned program flow changes using byte aligned addresses.
Claim 3
Dependent Claim
29 words
A system as recited in claim 1, wherein said instruction means comprises a code generator performing instruction expansion and code manipulations to align transfer target addresses on word boundaries.
Claim 4
Dependent Claim
33 words
A system as recited on claim 1, wherein said variable means comprises: an instruction queue receiving byte aligned instructions; and an alignment multiplexer coupled to said queue and aligning the instructions for execution.
Claim 5
Dependent Claim
56 words
A system as recited in claim 1, wherein said flow change means comprises: a program counter register designating addresses of instructions fetched; and an instruction address modification unit coupled to said program counter register and modifying a program counter using a word-aligned address when loading a scheduled program flow change address and a byte-aligned address otherwise.
Claim 6
Dependent Claim
22 words
A system as recited in claim 1, wherein in said processor, an instruction boundary is smaller than a memory system fetch boundary.
Claim 7
Dependent Claim
20 words
A system as recited in claim 1, wherein a branch address is on a memory fetch boundary of the processor.
Claim 8
Dependent Claim
16 words
A system as recited in claim 1, further comprising means for return branching into any instruction.
Claim 9
Dependent Claim
62 words
A system as recited in claim 1, further comprising: means for creating a symbol table which assigns a symbolic name for each jump target and a field indicating whether a final address must be aligned on a word boundary; and means for inserting a selected instruction when a jump target is encountered and a locator is not pointing to a word boundary.
Claim 10
Dependent Claim
76 words
A system as recited in claim 1, further comprising: means for scanning contiguous code to identify jump targets on byte boundaries; means for determining if any instruction prior to a target instruction can be expanded into an instruction that results in a word alignment for a respective target instruction; and means for expanding the instruction if any instruction is determined by said means for determining and for inserting a selected instruction if no instruction is determined.
Claim 11
Independent Claim
108 words
A system, comprising: a code generator performing instruction expansion and code manipulations to align transfer target addresses on word boundaries; and a processor, comprising: an instruction queue receiving byte aligned instructions; an alignment multiplexer coupled to said queue and aligning the instructions for execution; a program counter register designating addresses of instructions fetched; an instruction address modification unit coupled to said program counter register and modifying a program counter using a word-aligned address when loading a schedule program flow change address and using a byte-aligned address otherwise; transfer means for returning from unplanned program flow changes using byte aligned addresses; and execution means for executing the fetched instructions.
Claim 12
Independent Claim
108 words
A system, comprising: a code generator performing instruction expansion and code manipulations to align transfer target addresses on word boundaries; and a processor, comprising: an instruction queue receiving byte aligned instructions; an alignment multiplexer coupled to said queue and aligning the instructions for execution; a program counter register designating addresses of instructions fetched; an instruction address modification unit coupled to said program counter register and modifying a program counter using a word-aligned address when loading a schedule program flow change address and using a byte-aligned address otherwise; transfer means for returning from unplanned program flow changes using byte aligned addresses; and execution means for executing the fetched instructions.
Claim 13
Independent Claim
47 words
A method of executing computer instructions, comprising the steps of: a. aligning flow change target instructions on word boundaries; b. aligning sequentially executable instructions on byte boundaries; c. fetching and executing instructions using multiple byte fetching; and d. performing unplanned returns using byte aligned program transfer addresses.
Claim 14
Independent Claim
47 words
A method of executing computer instructions, comprising the steps of: a. aligning flow change target instructions on word boundaries; b. aligning sequentially executable instructions on byte boundaries; c. fetching and executing instructions using multiple byte fetching; and d. performing unplanned returns using byte aligned program transfer addresses.
References Cited (Backward Citations)
US4338663A
Cited
US4777594A
Cited
US4791557A
Cited
US5051885A
Cited
US5249273A
Cited
US5381532A
Cited
US5327536A
Cited
US5335332A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |