US5592631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus transaction reordering using side-band information signals
Assignee: Apple Inc
•
Filing: 1995-05-02
•
Granted: 1997-01-07
•
Expires: 2015-05-02
Abstract
Abstract The present invention, generally speaking, provides a system and method of decoupling the address and data buses of a system bus using side band information signals. A computer system with which the invention may be used has a system bus including an address bus and a data bus and has, operatively connected to said system bus, multiple master devices, including a microprocessor, and multiple slave devices. In accordance with one embodiment of the invention, the address bus and the data bus are decoupled by providing, in addition to signals carried by the system bus, first side-band signals including, for each master device besides the microprocessor, an address arbitration signal, and providing, in addition to signals carried by the system bus, second side-band signals including, for each slave device, an address termination signal, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus. An address arbitration vector is formed, composed of address arbitration signals for the master devices, an address termination vector is formed, composed of address termination signals for the slave devices, and a read-ready vector is formed, composed of read-ready signals for the slave devices. The address arbitration vector and the address termination vector are sampled. Using a queue structure having a front and a rear, pairs of address arbitration and address termination vectors sampled at different sampling times are queued. Given a pair of address arbitration and address termination vectors at the head of the queue structure and a subsequent, corresponding read-ready vector, a data arbitration signal is issued to one of the slave devices and one of the master devices, as a "paired data bus grant."
Inventors
- 👤 James D. Kelly
- 👤 R. Stephen Polzin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
209 words
A method of increasing bus utilization in a computer system having a system bus including an address bus and a data bus and having, operatively connected to said system bus, a plurality of master devices and a plurality of slave devices, said method comprising the steps of: providing a first plurality of signals including, for each master device an address arbitration signal; providing a second plurality of signals including, for each slave device, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus; providing a third plurality of signals including, for each slave device, an address termination signal; forming an address arbitration vector composed of address arbitration signals for said master devices, an address termination vector composed of address termination signals for said slave devices, and a read-ready vector composed of read-ready signals for said slave devices; sampling said address arbitration vector and said address termination vector; using a queue structure having a front and a rear, queuing address arbitration and address termination vectors; and issuing a data arbitration signal to one of said slave devices based on address arbitration and address termination vectors at the head of the queue structure and based on said read-ready vector.
Claim 2
Independent Claim
209 words
A method of increasing bus utilization in a computer system having a system bus including an address bus and a data bus and having, operatively connected to said system bus, a plurality of master devices and a plurality of slave devices, said method comprising the steps of: providing a first plurality of signals including, for each master device an address arbitration signal; providing a second plurality of signals including, for each slave device, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus; providing a third plurality of signals including, for each slave device, an address termination signal; forming an address arbitration vector composed of address arbitration signals for said master devices, an address termination vector composed of address termination signals for said slave devices, and a read-ready vector composed of read-ready signals for said slave devices; sampling said address arbitration vector and said address termination vector; using a queue structure having a front and a rear, queuing address arbitration and address termination vectors; and issuing a data arbitration signal to one of said slave devices based on address arbitration and address termination vectors at the head of the queue structure and based on said read-ready vector.
Claim 3
Dependent Claim
29 words
The method of claim 1, wherein said queuing step comprises providing separate master queues for each of said masters and providing separate slave queues for each of said slaves.
Claim 4
Dependent Claim
29 words
The method of claim 2, wherein said queuing step further comprises queuing said address termination vector in one of said separate master queues determined by said address arbitration vector.
Claim 5
Dependent Claim
29 words
The method of claim 3, wherein said queuing step further comprises queuing said address arbitration vector in one of said separate slave queues determined by said address termination vector.
Claim 6
Dependent Claim
66 words
The method of claim 4, wherein said issuing step comprises issuing said data arbitration signal to a matching one of said slave devices a separate slave queue of which has at a head thereof an address arbitration vector identifying one of said masters, a separate master queue of which in turn has at a head thereof an address termination vector identifying said one of said slaves.
Claim 7
Dependent Claim
41 words
The method of claim 5, wherein said issuing step further comprises delaying issuing said data arbitration signal to said one of said slave devices until said read-ready vector indicates that said slave device has data to present on the system bus.
Claim 8
Dependent Claim
86 words
The method of claim 5, wherein providing said first plurality of signals further comprises providing, for each master device, a data arbitration signal, and wherein said issuing step further comprises issuing a data arbitration signal to a matching one of said master devices a separate master queue of which has at a head thereof an address termination vector identifying one of said slaves, a separate slave queue of which in turn has at a head thereof an address arbitration vector identifying said one of said masters.
Claim 9
Dependent Claim
89 words
The method of claim 7, wherein said system bus includes at least one transfer type, signal whereby each of said address arbitration signals is associated with one of a read transaction and a write transaction, said issuing step comprising the further steps of: distinguishing between read transactions and write transactions; establishing a priority of said master devices; and for write transactions, if there are multiple matching ones of said master devices, issuing data arbitration signals to said multiple matching ones of said master devices in order of said priority.
Claim 10
Dependent Claim
10 words
The method of claim 8, wherein said priority is fixed.
Claim 11
Dependent Claim
36 words
The method of claim 1, wherein the computer system further comprises a microprocessor operatively connected to the system bus, and wherein the first and second pluralities of signals are side-band signals not connected to the microprocessor.
Claim 12
Independent Claim
185 words
A method of increasing bus utilization in a computer system having a system bus including an address bus and a data bus and having, operatively connected to said system bus, a plurality of master devices and a plurality of slave devices, said method comprising the steps of: providing a first plurality of signals including, for each master device an address arbitration signal; establishing a priority of said master devices; providing a second plurality of signals including, for each slave device, a data arbitration signal; providing a third plurality of signals including, for each slave device, an address termination signal; forming an address arbitration vector composed of address arbitration signals for said master devices, an address termination vector composed of address termination signals for said slave devices; sampling said address arbitration vector and said address termination vector; using a queue structure having a front and a rear, queuing address arbitration and address termination vectors; and issuing a data arbitration signal to one of said slave devices based on address arbitration and address termination vectors at the head of the queue structure and based on said priority.
Claim 13
Independent Claim
185 words
A method of increasing bus utilization in a computer system having a system bus including an address bus and a data bus and having, operatively connected to said system bus, a plurality of master devices and a plurality of slave devices, said method comprising the steps of: providing a first plurality of signals including, for each master device an address arbitration signal; establishing a priority of said master devices; providing a second plurality of signals including, for each slave device, a data arbitration signal; providing a third plurality of signals including, for each slave device, an address termination signal; forming an address arbitration vector composed of address arbitration signals for said master devices, an address termination vector composed of address termination signals for said slave devices; sampling said address arbitration vector and said address termination vector; using a queue structure having a front and a rear, queuing address arbitration and address termination vectors; and issuing a data arbitration signal to one of said slave devices based on address arbitration and address termination vectors at the head of the queue structure and based on said priority.
Claim 14
Dependent Claim
36 words
The method of claim 11, wherein the computer system further comprises a microprocessor operatively connected to the system bus, and wherein the first and second pluralities of signals are side-band signals not connected to the microprocessor.
Claim 15
Dependent Claim
210 words
A computer system comprising: a system bus including an address bus and a data bus; a plurality of master devices operatively connected to said system bus; a plurality of slave devices operatively connected to said system bus; a first plurality of signals including, for each master device, an address arbitration signal; a second plurality of signals including, for each slave device, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus; a third plurality of signals including, for each slave device, an address termination signal; a central arbiter for arbitrating access to the system bus between said master devices and said slave devices, said arbiter comprising: means for sampling an address arbitration vector composed of address arbitration signals for said master devices and an address termination vector composed of address termination signals for said slave devices; a queue structure having a front and a rear, including means for queuing address arbitration and address termination vectors; and means for issuing a data arbitration signal to one of said slave devices based on address arbitration and address termination vectors at the head of the queue structure and based on a read-ready vector composed of read-ready signals for said slave devices.
Claim 16
Dependent Claim
210 words
A computer system comprising: a system bus including an address bus and a data bus; a plurality of master devices operatively connected to said system bus; a plurality of slave devices operatively connected to said system bus; a first plurality of signals including, for each master device, an address arbitration signal; a second plurality of signals including, for each slave device, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus; a third plurality of signals including, for each slave device, an address termination signal; a central arbiter for arbitrating access to the system bus between said master devices and said slave devices, said arbiter comprising: means for sampling an address arbitration vector composed of address arbitration signals for said master devices and an address termination vector composed of address termination signals for said slave devices; a queue structure having a front and a rear, including means for queuing address arbitration and address termination vectors; and means for issuing a data arbitration signal to one of said slave devices based on address arbitration and address termination vectors at the head of the queue structure and based on a read-ready vector composed of read-ready signals for said slave devices.
Claim 17
Dependent Claim
36 words
The system of claim 13, wherein the computer system further comprises a microprocessor operatively connected to the system bus, and wherein the first and second pluralities of signals are side-band signals not connected to the microprocessor.
Claim 18
Dependent Claim
173 words
A computer system comprising: a system bus including an address bus and a data bus a plurality of master devices operatively connected to said system bus; a plurality of slave devices operatively connected to said system bus; a first plurality of signals including at least one signal for each master device; a second plurality of signals including at least first and second side-band signals for each slave device; a central arbiter for arbitrating access to the system bus between said master devices and said slave devices, said arbiter comprising: means for sampling said first plurality of signals to produce a first signal vector and for sampling said second plurality of signals to produce second and third signal vectors; a queue structure having a front and a rear, including means for queuing said first and second signal vectors; and means for issuing a data arbitration signal to one of said slave devices based on said first and second signal vectors at the head of the queue structure and based on said third signal vector.
Claim 19
Dependent Claim
173 words
A computer system comprising: a system bus including an address bus and a data bus a plurality of master devices operatively connected to said system bus; a plurality of slave devices operatively connected to said system bus; a first plurality of signals including at least one signal for each master device; a second plurality of signals including at least first and second side-band signals for each slave device; a central arbiter for arbitrating access to the system bus between said master devices and said slave devices, said arbiter comprising: means for sampling said first plurality of signals to produce a first signal vector and for sampling said second plurality of signals to produce second and third signal vectors; a queue structure having a front and a rear, including means for queuing said first and second signal vectors; and means for issuing a data arbitration signal to one of said slave devices based on said first and second signal vectors at the head of the queue structure and based on said third signal vector.
Claim 20
Dependent Claim
36 words
The system of claim 15, wherein the computer system further comprises a microprocessor operatively connected to the system bus, and wherein the first and second pluralities of signals are side-band signals not connected to the microprocessor.
References Cited (Backward Citations)
US4181974A
Cited
US4473880A
Cited
US4965716A
Cited
US5327538A
Cited
US5375215A
Cited
US5191649A
Cited
US5257356A
Cited
US5287477A
Cited
US5345562A
Cited
US5473762A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |