Method and apparatus for optimizing supervisor mode store operations in a data cache

Claim 2

In a computer system comprising a processor and memory hierarchy, said memory hierarchy including a main memory and a data cache, said processor executing code including memory operations while in one of a plurality of modes, said modes including a supervisor mode, an apparatus for performing conditional cache allocate operations on data when a cache miss on a store operation occurs, said apparatus comprising: cacheable status indicative of whether the data is cacheable; mode status indicative of whether the operation is being performed while the processor is in supervisor mode; a data cache controller for controlling read and write operations to the cache, aid data cache controller receiving a cacheable signal by which data is identified to be cacheable and non-cacheable, said data cache controller performing a cache allocate operation if the data is cacheable; a memory management unit coupled to receive a memory address on which to perform the memory operation, wherein if a store miss occurs, said memory management unit checks the state of the mode status to determine whether the operation is being performed while in supervisor mode, said memory management unit sue a cacheable signal to the data cache controller indicating that the data is non-cacheable if the memory management unit determines that the processor is in supervisor mode, if the mode status indicates that the processor is not in supervisor mode, said memory management unit issues a cacheable signal to the data cache controller indicating that the data is non-cacheable if the cacheable status indicates that the data is non-cacheable and issues a cacheable signal indicating that the data is cacheable if the cacheable status indicates that the data is cacheable; wherein cache allocate operations are eliminated while the processor in supervisor mode.

Claim 3

The apparatus as set forth in claim 1, wherein said memory management unit stores-the cacheable status.

Claim 4

The apparatus as set forth in claim 1 wherein the mode status is stored in a processor status register located in the processor, said memory management unit performing a read of the processor status register to determine whether the processor is in supervisor mode.

Claim 5

The apparatus as set forth in claim 1, wherein said memory management unit further comprises a translation look aside buffer comprising a page table, said page table comprising page table entries, each page table entry including a bit identifying the cacheable status indicative of whether data corresponding to the page table entry is cacheable.

Claim 6

In a computer system comprising a processor and memory hierarchy, said memory hierarchy including a main memory and a data cache, said processor executing code including memory operations while in one of a plurality of modes, said modes including a supervisor mode, an apparatus for performing conditional cache allocate operations on data when a cache miss on a store operation occurs, said apparatus comprising: a processor status register located in the processor, said processor status register storing status information indicative of whether the operation is being performed while the processor is in supervisor mode; a data cache controller for controlling read and write operations to the cache, said data cache controller receiving a cacheable signal by which data is identified to be cacheable and non-cacheable, said data cache controller performing a cache allocate operation if the data is cacheable; a memory management unit coupled to receive a memory address on which to perform the memory operation, said memory management unit comprising; a translation look aside buffer comprising a page table, said page table including page table entries identified according to a corresponding memory address, each page table entry comprising a cacheable status bit indicative of whether the corresponding page of memory is cacheable, mode status determination mechanism to read the processor status register when a store miss occurs, signal generator for generating the cacheable signal to the data cache controller, said signal generator issuing a cacheable signal indicating that the data is non-cacheable if the mode status determination mechanism determines that the processor is in supervisor mode, if it is determined that the processor is not in supervisor mode, said memory management unit issuing a cacheable signal to the data cache controller indicating that the data is non-cacheable if the cacheable status bit in the corresponding page table entry indicates that the data is non-cacheable and issuing a cacheable signal indicating that the data is cacheable if the cacheable status bit indicates that the data is cacheable; wherein cache allocate operations are eliminated while the processor in supervisor mode.

Claim 7

In a computer system comprising a processor and memory hierarchy, said memory hierarchy including a main memory and a data cache, said processor executing code including memory operations while in one of a plurality of modes, said modes including a supervisor mode, an apparatus for performing conditional cache allocate operations on data when a cache miss on a store operation occurs, said apparatus comprising: a processor status register located in the processor, said processor status register storing status information indicative of whether the operation is being performed while the processor is in supervisor mode; a data cache controller for controlling read and write operations to the cache, said data cache controller receiving a cacheable signal by which data is identified to be cacheable and non-cacheable, said data cache controller performing a cache allocate operation if the data is cacheable; a memory management unit coupled to receive a memory address on which to perform the memory operation, said memory management unit comprising; a translation look aside buffer comprising a page table, said page table including page table entries identified according to a corresponding memory address, each page table entry comprising a cacheable status bit indicative of whether the corresponding page of memory is cacheable, mode status determination mechanism to read the processor status register when a store miss occurs, signal generator for generating the cacheable signal to the data cache controller, said signal generator issuing a cacheable signal indicating that the data is non-cacheable if the mode status determination mechanism determines that the processor is in supervisor mode, if it is determined that the processor is not in supervisor mode, said memory management unit issuing a cacheable signal to the data cache controller indicating that the data is non-cacheable if the cacheable status bit in the corresponding page table entry indicates that the data is non-cacheable and issuing a cacheable signal indicating that the data is cacheable if the cacheable status bit indicates that the data is cacheable; wherein cache allocate operations are eliminated while the processor in supervisor mode.

Claim 8

In a computer system comprising a processor and memory hierarchy, said memory hierarchy including a main memory and a data cache, said processor executing code including memory operations while in one of a plurality of modes, said modes including a supervisor mode, a method for performing conditional cache allocate operations on data when a cache miss on a store operation occurs, said method comprising the steps of: storing cacheable status indicative of whether data is cacheable; storing mode status indicative of whether the operation is being performed while the processor is in supervisor mode; if a miss to the data cache occurs during a store operation; checking the mode status indicative of whether the operation is being performed while the processor is in supervisor mode, if the processor is in supervisor mode, issuing a cacheable signal indicating that the data is not cacheable, and if the processor is not in supervisor mode, checking the cacheable status to determine whether the data is cacheable, if the data is cacheable, issuing a cacheable signal indicating that the data is cacheable, and if the data is not cacheable, issuing a cacheable signal indicating that the data is not cacheable; and performing a write allocate operation if the data is cacheable; wherein cache allocate operations are eliminated while the processor in supervisor mode.

Claim 9

In a computer system comprising a processor and memory hierarchy, said memory hierarchy including a main memory and a data cache, said processor executing code including memory operations while in one of a plurality of modes, said modes including a supervisor mode, a method for performing conditional cache allocate operations on data when a cache miss on a store operation occurs, said method comprising the steps of: storing cacheable status indicative of whether data is cacheable; storing mode status indicative of whether the operation is being performed while the processor is in supervisor mode; if a miss to the data cache occurs during a store operation; checking the mode status indicative of whether the operation is being performed while the processor is in supervisor mode, if the processor is in supervisor mode, issuing a cacheable signal indicating that the data is not cacheable, and if the processor is not in supervisor mode, checking the cacheable status to determine whether the data is cacheable, if the data is cacheable, issuing a cacheable signal indicating that the data is cacheable, and if the data is not cacheable, issuing a cacheable signal indicating that the data is not cacheable; and performing a write allocate operation if the data is cacheable; wherein cache allocate operations are eliminated while the processor in supervisor mode.

Claim 10

The method as set forth in claim 6, wherein said step of storing cacheable status comprises the step of generating page table entries in a page table in a translation look aside buffer, each page table entry corresponding to a page of memory and includes a status bit indicative of whether the page is cacheable.

Claim 11

The method as set forth in claim 6, wherein said step of storing mode status comprises the step of providing a processor status register in the processor, said processor status register containing identification of the mode.

Claim 12

The method as set forth in claim 8, wherein said step of checking the mode status comprises the step of reading the processor status register.

Claim 13

The method as set forth in claim 6, wherein the steps of issuing a cacheable signal issues the signal to a data cache controller which controls operations to the cache, including a cache allocate operation.

Claim 14

The method as set forth in claim 7, wherein the step of checking the cacheable status comprises the step of locating the corresponding page table entry and reading the cacheable status bit indicative of whether the page is cacheable.