Patent US5606696A successfully refreshed from Google Patents.
US5606696A
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Exception handling method and apparatus for a microkernel data processing system
Assignee: International Business Machines Corp
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Filing: 1995-09-25
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Granted: 1997-02-25
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Expires: 2015-09-25
Abstract
Abstract Floating point hardware register set is not given to any user level thread unless it is required to perform floating point operations. Thus, for any non-floating thread, its context does not include the floating point hardware state. This effectively reduces the amount of information to be handled when threads are swapped in the processor. During the course of a thread's execution, at the first instance of an attempt by the thread to execute a floating point instruction, the "float-unavailable" exception occurs. This, in turn, invokes the microkernel's floating point exception handler. The function of this exception handler is to make floating point available to the thread that requires it. The exception handler dynamically allocates space for saving the thread's floating point registers, initializes the registers, and turns on the "float-available" bit in its machine state register. Once a thread obtains floating point context, it continues to have it for the remainder of its life.
Inventors
- 👤 Dennis F. Ackerman
- 👤 Himanshu H. Desai
- 👤 Ram K. Gupta
- 👤 Ravi R. Srinivasan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/461; G06F9/4843; G06F2209/00; G06F2209/48; G06F2209/481
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
547 words
An article of manufacture for use in a data processing system including a memory and a processor that has a plurality of fixed point registers and a plurality of floating point registers, comprising: a computer useable medium having computer readable program code means embodied therein for providing a method for managing process threads that are to be executed by the processor, the computer readable program code means in said article of manufacture comprising: computer readable program code means for causing a computer to create a process thread in the memory to be executed by the processor, and a process control block in the memory to store thread information; computer readable program code means for causing a computer to store in the process control block a non-floating point indication that the process thread is not enabled to perform floating point operations; computer readable program code means for causing a computer to execute during a first occurring session, only fixed point operations with the process thread in the processor using the plurality of fixed point registers; computer readable program code means for causing a computer to remove the process thread from the processor at a termination of the first session and storing first values of the fixed point registers in the process control block and, in response to said non-floating point indication, not storing the contents of the plurality of floating point registers in the process control block; computer readable program code means for causing a computer to restore the execution of the thread in the processor in a second occurring session by detecting said non-floating point indication in the process control block, and in response thereto, performing a lazy context restore operation by loading said first values from the process control block into the plurality of fixed point registers and not loading the plurality of floating point registers of the processor; computer readable program code means for causing a computer to execute during said second occurring session, fixed point operations with the process thread in the processor using the plurality of fixed point registers; computer readable program code means for causing a computer to attempt to execute a floating point instruction in the process thread during said second session, and in response thereto, calling an exception handler; computer readable program code means for causing a computer to use said exception handler to store an alternate floating point indication in the process control block, to indicate that the process thread is enabled to perform floating point operations; computer readable program code means for causing a computer to resume execution of said floating point instruction in the process thread; computer readable program code means for causing a computer to remove the process thread from the processor at a termination of said second session and storing second values of the plurality of floating point registers in the process control block in response to said alternate floating point indication; and computer readable program code means for causing a computer to restore the execution of the process thread in the processor in a third occurring session by detecting said alternate floating point indication, and in response thereto, performing a lazy context restore operation by loading said second values from the process control block into the plurality of floating point registers of the processor.
Claim 2
Dependent Claim
547 words
An article of manufacture for use in a data processing system including a memory and a processor that has a plurality of fixed point registers and a plurality of floating point registers, comprising: a computer useable medium having computer readable program code means embodied therein for providing a method for managing process threads that are to be executed by the processor, the computer readable program code means in said article of manufacture comprising: computer readable program code means for causing a computer to create a process thread in the memory to be executed by the processor, and a process control block in the memory to store thread information; computer readable program code means for causing a computer to store in the process control block a non-floating point indication that the process thread is not enabled to perform floating point operations; computer readable program code means for causing a computer to execute during a first occurring session, only fixed point operations with the process thread in the processor using the plurality of fixed point registers; computer readable program code means for causing a computer to remove the process thread from the processor at a termination of the first session and storing first values of the fixed point registers in the process control block and, in response to said non-floating point indication, not storing the contents of the plurality of floating point registers in the process control block; computer readable program code means for causing a computer to restore the execution of the thread in the processor in a second occurring session by detecting said non-floating point indication in the process control block, and in response thereto, performing a lazy context restore operation by loading said first values from the process control block into the plurality of fixed point registers and not loading the plurality of floating point registers of the processor; computer readable program code means for causing a computer to execute during said second occurring session, fixed point operations with the process thread in the processor using the plurality of fixed point registers; computer readable program code means for causing a computer to attempt to execute a floating point instruction in the process thread during said second session, and in response thereto, calling an exception handler; computer readable program code means for causing a computer to use said exception handler to store an alternate floating point indication in the process control block, to indicate that the process thread is enabled to perform floating point operations; computer readable program code means for causing a computer to resume execution of said floating point instruction in the process thread; computer readable program code means for causing a computer to remove the process thread from the processor at a termination of said second session and storing second values of the plurality of floating point registers in the process control block in response to said alternate floating point indication; and computer readable program code means for causing a computer to restore the execution of the process thread in the processor in a third occurring session by detecting said alternate floating point indication, and in response thereto, performing a lazy context restore operation by loading said second values from the process control block into the plurality of floating point registers of the processor.
Claim 3
Dependent Claim
598 words
An article of manufacture for use in a data processing system including a memory, a first processor that has a first plurality of fixed point registers and a first plurality of floating point registers, a second processor that has a second plurality of fixed point registers and a second plurality of floating point registers, comprising: a computer useable medium having computer readable program code means embodied therein for providing a method for managing a process thread that is to be executed by the processors, the computer readable program code means in said article of manufacture comprising: computer readable program code means for causing a computer to create the process thread in the memory to be executed by the first processor, and a process control block in the memory to store thread information; computer readable program code means for causing a computer to store in the process control block a non-floating point indication that the process thread is not enabled to perform floating point operations; computer readable program code means for causing a computer to execute during a first occurring session, only fixed point operations with the process thread in the first processor using the first plurality of fixed point registers; computer readable program code means for causing a computer to remove the thread from the first processor at a termination of the first session and storing first values of the first plurality of fixed point registers in the process control block and, in response to said non-floating point indication, not storing the contents of the first plurality of floating point registers in the process control block; computer readable program code means for causing a computer to restore the execution of the process thread in the second processor in a second occurring session by detecting said non-floating point indication in the process control block, and in response thereto, performing a lazy context restore operation by loading said first values from the process control block into the second plurality of fixed point registers and not loading the second plurality of floating point registers of the second processor; computer readable program code means for causing a computer to execute during said second occurring session, fixed point operations with the process thread in the second processor using the second plurality of fixed point registers; computer readable program code means for causing a computer to attempt to execute a floating point instruction in the process thread during said second session, and in response thereto, calling an exception handler; computer readable program code means for causing a computer to use said exception handler to store an alternate floating point indication in the process control block, to indicate that the process thread is enabled to perform floating point operations; computer readable program code means for causing a computer to resume execution of said floating point instruction in the process thread in the second processor; computer readable program code means for causing a computer to remove the process thread from the second processor at a termination of said second session and storing second values of the second plurality of floating point registers in the process control block in response to said alternate floating point indication; and computer readable program code means for causing a computer to restore the execution of the process thread in the second processor in a third occurring session by detecting said alternate floating point indication in the process control block, and in response thereto, performing a lazy context restore operation by loading said second values from the process control block into the second plurality of floating point registers of the second processor.
Claim 4
Dependent Claim
598 words
An article of manufacture for use in a data processing system including a memory, a first processor that has a first plurality of fixed point registers and a first plurality of floating point registers, a second processor that has a second plurality of fixed point registers and a second plurality of floating point registers, comprising: a computer useable medium having computer readable program code means embodied therein for providing a method for managing a process thread that is to be executed by the processors, the computer readable program code means in said article of manufacture comprising: computer readable program code means for causing a computer to create the process thread in the memory to be executed by the first processor, and a process control block in the memory to store thread information; computer readable program code means for causing a computer to store in the process control block a non-floating point indication that the process thread is not enabled to perform floating point operations; computer readable program code means for causing a computer to execute during a first occurring session, only fixed point operations with the process thread in the first processor using the first plurality of fixed point registers; computer readable program code means for causing a computer to remove the thread from the first processor at a termination of the first session and storing first values of the first plurality of fixed point registers in the process control block and, in response to said non-floating point indication, not storing the contents of the first plurality of floating point registers in the process control block; computer readable program code means for causing a computer to restore the execution of the process thread in the second processor in a second occurring session by detecting said non-floating point indication in the process control block, and in response thereto, performing a lazy context restore operation by loading said first values from the process control block into the second plurality of fixed point registers and not loading the second plurality of floating point registers of the second processor; computer readable program code means for causing a computer to execute during said second occurring session, fixed point operations with the process thread in the second processor using the second plurality of fixed point registers; computer readable program code means for causing a computer to attempt to execute a floating point instruction in the process thread during said second session, and in response thereto, calling an exception handler; computer readable program code means for causing a computer to use said exception handler to store an alternate floating point indication in the process control block, to indicate that the process thread is enabled to perform floating point operations; computer readable program code means for causing a computer to resume execution of said floating point instruction in the process thread in the second processor; computer readable program code means for causing a computer to remove the process thread from the second processor at a termination of said second session and storing second values of the second plurality of floating point registers in the process control block in response to said alternate floating point indication; and computer readable program code means for causing a computer to restore the execution of the process thread in the second processor in a third occurring session by detecting said alternate floating point indication in the process control block, and in response thereto, performing a lazy context restore operation by loading said second values from the process control block into the second plurality of floating point registers of the second processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |