Fast internal reference cell trimming for flash EEPROM memory

Claim 2

A circuit for programming a non-volatile memory cell such that the non-volatile memory cell stores close to a target amount of charge, comprising: a voltage switch coupled to a gate of the non-volatile memory cell; and a controller coupled to the voltage switch for controlling the voltage switch to apply charging pulses to the gate of the non-volatile memory cell until the non-volatile memory cell stores close to the target amount of charge, the controller controlling the voltage switch by causing the voltage switch to apply a first charging pulse having a first charging voltage to the non-volatile memory cell for a first duration such that the non-volatile memory cell stores a first amount of charge that is less than the target amount of charge; causing the voltage switch to apply a second set of charging pulses to the non-volatile memory cell such that the non-volatile memory cell stores a second amount of charge that is less than the target amount of charge and greater than the first amount of charge, wherein each charging pulse of the second set of charging pulses is applied for a second duration that is less than the first duration, the controller causing the voltage switch to increase a second charging voltage of each charging pulse over an immediately previous pulse; and causing the voltage switch to apply a third set of charging pulses to the non-volatile memory cell such that the non-volatile memory cell stores a third amount of charge that is within an allowable variation of the target amount of charge, wherein each charging pulse of the third set of charging pulses is applied for a third duration that is less than the second duration.

Claim 3

The circuit of claim 1, further comprising: a sense amplifier having a first terminal coupled to a drain of the non-volatile memory cell and a second terminal; a circuit for supplying a reference voltage to the second terminal of the sense amplifier, the controller selecting a first value for the reference voltage, the first value corresponding to a memory cell that stores the second amount of charge, after applying the first charging pulse, the controller closing the switch and the sense amplifier testing the non-volatile memory cell in response to the switch closing to determine whether the first amount of charge exceeds the second amount of charge, wherein the step of applying the second set of charging pulses is not performed if the first amount of charge exceeds the second amount of charge, after applying each charging pulse of the second set of charging pulses, the controller closing the switch and the sense amplifier testing the non-volatile memory cell to determine whether the non-volatile memory cell stores the second amount of charge, wherein the charging pulses of the second set of charging pulses continue to be applied until the non-volatile memory cell is determined as storing the second amount of charge, the controller selecting a second value for the reference voltage after the non-volatile memory cell is determined as storing the second amount of charge, the second value corresponding to a memory cell that stores the third amount of charge; after applying each charging pulse of the third set of charging pulses, the controller closing the switch and the sense amplifier testing the non-volatile memory cell to determine whether the non-volatile memory cell stores the third amount of charge, wherein the charging pulses of the third set of charging pulses continue to be applied until the non-volatile memory cell is determined as storing the third amount of charge, wherein the controller opens the switch after each testing step.

Claim 4

The circuit of claim 1, wherein a charging voltage of each charging pulse of the second set of charging pulses is greater than a charging voltage of an immediately previous charging pulse.

Claim 5

The circuit of claim 1, wherein the first charging voltage and the first duration are selected such that a flash EEPROM memory cell is placed in a saturation range.

Claim 6

The circuit of claim 1, wherein the second duration is approximately one-fourth the first duration, and the third duration is approximately one-tenth the second duration.

Claim 7

The circuit of claim 5, wherein a charging voltage of each charging pulse of the second set of charging pulses is one-tenth volt greater than a charging voltage of an immediately previous charging pulse.