Patent US5608739A successfully refreshed from Google Patents.
US5608739A
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US
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Apparatus and method for error detection and correction in radio frequency identification device
Assignee: Round Rock Research LLC
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Filing: 1995-09-08
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Granted: 1997-03-04
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Expires: 2015-09-08
Abstract
Abstract An RF identification system has a forward link that includes an encoder and decoder that utilize an (8, 13, 4) block code. The (8, 13, 4) block code has the ability to detect one bad bit in a thirteen-bit block, and can always detect two bad bits per block.
Inventors
- 👤 Charles K. Snodgrass
- 👤 Armando Montalvo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:52
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; H03M13/151; H04L1/0041; H04L1/0043; H04L1/0045; H04L1/0052; H04L1/12; H04L1/16; H04L1/18
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
195 words
A radio frequency identification system comprising: a source of an information signal having eight-bit blocks; (8, 13, 4) block code encoder means responsive to the information signal for providing a linear systematic block coded signal comprising a coded block having eight information bits and five code bits for each of the eight-bit blocks; transmitter means responsive to the thirteen-bit linear systematic block coded signal for providing a transmitted signal; receiver means responsive to the transmitted signal for providing a signal comprising received coded blocks; (8, 13, 4) linear systematic block code decoder means for decoding the received coded blocks to provide a decoded signal comprising one eight-bit decoded block for each of the received coded blocks, the eight-bit decoded blocks being generated each time there are less than two bit errors in a received coded block; means within the decoder for determining if there are exactly two bit errors in any of the received coded blocks; means within the decoder for correcting one bit error operable each time only one bit error occurs in any of the received coded blocks; and identifier means responsive to the eight-bit decoded blocks for providing a return identification signal.
Claim 2
Dependent Claim
195 words
A radio frequency identification system comprising: a source of an information signal having eight-bit blocks; (8, 13, 4) block code encoder means responsive to the information signal for providing a linear systematic block coded signal comprising a coded block having eight information bits and five code bits for each of the eight-bit blocks; transmitter means responsive to the thirteen-bit linear systematic block coded signal for providing a transmitted signal; receiver means responsive to the transmitted signal for providing a signal comprising received coded blocks; (8, 13, 4) linear systematic block code decoder means for decoding the received coded blocks to provide a decoded signal comprising one eight-bit decoded block for each of the received coded blocks, the eight-bit decoded blocks being generated each time there are less than two bit errors in a received coded block; means within the decoder for determining if there are exactly two bit errors in any of the received coded blocks; means within the decoder for correcting one bit error operable each time only one bit error occurs in any of the received coded blocks; and identifier means responsive to the eight-bit decoded blocks for providing a return identification signal.
Claim 3
Dependent Claim
55 words
A radio frequency identification system as in claim 1 wherein the decoder means further comprises: syndrome generator means responsive to the transmitted signal for providing a syndrome signal; and error detection circuit means responsive to the means for determining for providing a signal indicative that a noncorrectable error in the transmitted signal has been detected.
Claim 4
Dependent Claim
82 words
A radio frequency identification system as in claim 1 wherein the first eight bits of the coded signal comprise the eight bits, i 1 , i 2 , i 3 , i 4 , i 5 , i 6 , i 7 , and i 8 , of the information signal, and the last five bits of the coded signal comprise a first parity bit, a second parity bit, a third parity bit, a fourth parity bit, and a fifth parity bit.
Claim 5
Dependent Claim
131 words
A communication error detection and correction system comprising: a source of an information signal having eight-bit blocks; (8, 13, 4) block code encoder means responsive to the information signal for providing a systematic block coded signal comprising thirteen-bit blocks for each eight-bit block of the information signal; communication means responsive to the linear systematic block coded signal for providing a communicated signal; and (8, 13, 4) linear systematic block code decoder means for decoding the communicated signal to provide a decoded signal having an eight-bit decoded block for each eight-bit block of the information signal, wherein the decoder means further comprises error detection circuit means for providing a signal indicative that a noncorrectable error in the communicated signal has been detected, wherein the error detection circuit means comprises eleven logic gates.
Claim 6
Dependent Claim
131 words
A communication error detection and correction system comprising: a source of an information signal having eight-bit blocks; (8, 13, 4) block code encoder means responsive to the information signal for providing a systematic block coded signal comprising thirteen-bit blocks for each eight-bit block of the information signal; communication means responsive to the linear systematic block coded signal for providing a communicated signal; and (8, 13, 4) linear systematic block code decoder means for decoding the communicated signal to provide a decoded signal having an eight-bit decoded block for each eight-bit block of the information signal, wherein the decoder means further comprises error detection circuit means for providing a signal indicative that a noncorrectable error in the communicated signal has been detected, wherein the error detection circuit means comprises eleven logic gates.
Claim 7
Dependent Claim
29 words
A communication error detection and correction system as in claim 4 wherein the eleven logic gates comprise two exclusive-OR gates, three inverters, five AND gates, and an OR gate.
Claim 8
Dependent Claim
130 words
A radio frequency identification circuit for receiving a transmitted thirteen-bit linear systematic block coded signal comprising: memory for storing an identification code; a linear systematic (8, 13, 4) block code decoder means responsive to the thirteen-bit coded signal for providing a decoded signal comprising eight-bits for each block of the transmitted coded signal; a syndrome generator responsive to the transmitted signal for providing a syndrome signal; and an error detection circuit responsive to the syndrome signal for providing a signal indicative that a noncorrectable error in the transmitted signal has been detected; and identifier means responsive to the decoded signal for providing a return identification signal when the decoded signal matches the stored identification code, the identifier means being disabled in response to the signal from the error detection circuit.
Claim 9
Dependent Claim
130 words
A radio frequency identification circuit for receiving a transmitted thirteen-bit linear systematic block coded signal comprising: memory for storing an identification code; a linear systematic (8, 13, 4) block code decoder means responsive to the thirteen-bit coded signal for providing a decoded signal comprising eight-bits for each block of the transmitted coded signal; a syndrome generator responsive to the transmitted signal for providing a syndrome signal; and an error detection circuit responsive to the syndrome signal for providing a signal indicative that a noncorrectable error in the transmitted signal has been detected; and identifier means responsive to the decoded signal for providing a return identification signal when the decoded signal matches the stored identification code, the identifier means being disabled in response to the signal from the error detection circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |