Memory bandwidth optimization

Claim 2

A memory controller apparatus for processing data and reducing an effect of non-aligned page misses during page mode memory access, comprising: an input port for receiving data; an input FIFO coupled to said input port for receiving and storing said data; a memory coupled to said input FIFO for receiving said data from at least said input FIFO and for storing said data; an output FIFO coupled to said memory and a control means for retrieving and storing at least a portion of said data; an output port, coupled to said output FIFO for receiving and outputting said at least a portion of said data from said output FIFO; and said control means, coupled to said input FIFO and said memory, for controlling page mode access to said memory in at least input cycles, wherein said control means controls said input FIFO to transfer data in a first predetermined number of memory cycles from said input FIFO to said memory during an input cycle, said control means monitors said memory cycles during said input cycle to detect a non-aligned memory cycle and interrupts an input cycle if a non-aligned memory cycle is detected, said control means further controls said output FIFO to transfer data during a second predetermined number of memory cycles from said memory to said output FIFO during an output cycle, said control means monitors said memory cycles during said output cycle to detect a non-aligned memory cycle and shortens a subsequent input cycle if a non-aligned memory cycle is detected, and said control means shortens a subsequent input cycle by reducing said first predetermined number of memory cycles in a subsequent input cycle.

Claim 3

A video controller integrated circuit for selectively generating video and graphics data for displaying a video image on at least a portion of a graphics display and reducing an effect of non-aligned page misses during page mode memory access, said video controller integrated circuit comprising: a video port for receiving video data; a video port FIFO coupled to said video port for receiving and storing said video data; a display memory bus coupled to said video port FIFO for receiving said video data from at least said video port FIFO and for storing said video data in a display memory; and a CRT FIFO coupled to said display memory bus and a control means for retrieving and storing at least a portion of said video data from a display memory; an output port, coupled to said CRT FIFO for receiving and outputting said at least a portion of said video data from said CRT FIFO; and said control means, coupled to said video port FIFO and said display memory bus, for controlling page mode access to said display memory bus in video port FIFO cycles, wherein said control means controls said video port FIFO to transfer video data during a first predetermined number of memory cycles from said video port FIFO to said display memory bus during a video port FIFO cycle, said control means monitors said memory cycles during said video port FIFO cycle to detect a non-aligned memory cycle and interrupts a video port FIFO cycle if a non-aligned memory cycle is detected, said control means further controls said CRT FIFO to transfer video data during a second predetermined number of memory cycles from said display memory bus to said CRT FIFO during a CRT FIFO cycle, said control means monitors said memory cycles during said CRT FIFO cycle to detect a non-aligned memory cycle and shortens a subsequent video port FIFO cycle if a non-aligned memory cycle is detected, and said control means shortens said subsequent video-port FIFO cycle by reducing said first predetermined number of memory cycles in a subsequent video port FIFO cycle.

Claim 4

A video controller integrated circuit for selectively generating video and graphics data for displaying a video image on at least a portion of a graphics display and reducing an effect of non-aligned page misses during page mode memory access, said video controller integrated circuit comprising: a video port for receiving video data; a video port FIFO coupled to said video port for receiving and storing said video data; a display memory bus coupled to said video port FIFO for receiving said video data from at least said video port FIFO and for storing said video data in a display memory; and a CRT FIFO coupled to said display memory bus and a control means for retrieving and storing at least a portion of said video data from a display memory; an output port, coupled to said CRT FIFO for receiving and outputting said at least a portion of said video data from said CRT FIFO; and said control means, coupled to said video port FIFO and said display memory bus, for controlling page mode access to said display memory bus in video port FIFO cycles, wherein said control means controls said video port FIFO to transfer video data during a first predetermined number of memory cycles from said video port FIFO to said display memory bus during a video port FIFO cycle, said control means monitors said memory cycles during said video port FIFO cycle to detect a non-aligned memory cycle and interrupts a video port FIFO cycle if a non-aligned memory cycle is detected, said control means further controls said CRT FIFO to transfer video data during a second predetermined number of memory cycles from said display memory bus to said CRT FIFO during a CRT FIFO cycle, said control means monitors said memory cycles during said CRT FIFO cycle to detect a non-aligned memory cycle and shortens a subsequent video port FIFO cycle if a non-aligned memory cycle is detected, and said control means shortens said subsequent video-port FIFO cycle by reducing said first predetermined number of memory cycles in a subsequent video port FIFO cycle.

Claim 5

The video controller integrated circuit of claim 2, further comprising: a CPU input port for connecting to an external CPU and for receiving text and graphics data from an external CPU; and a text and graphics controller coupled to said CPU input port and said control means for receiving text and graphics data; wherein said control means transfers text and graphics data from said text and graphics controller to said display memory during a CPU cycle.

Claim 6

The video controller integrated circuit of claim 2, wherein said control means transfers data accumulated in said video port FIFO when said control means interrupts an video port FIFO cycle to said display memory during a retrace interval of said video data from said video port.

Claim 7

A multimedia computer system for selectively generating video and graphics data for displaying a video image on at least a portion of a display and reducing an effect of non-aligned page misses during page mode memory access, said multimedia computer system comprising: a video port for receiving video data; a video port FIFO coupled to said video port for receiving and storing said video data; a display memory coupled to said video port FIFO for receiving said video data from at least said video port FIFO and for storing said video data; and a CRT FIFO coupled to said display memory and a control means for retrieving and storing at least a portion of said video data from a display memory; an output display port, coupled to said CRT FIFO for receiving and outputting said at least a portion of said video data from said CRT FIFO; and said control means, coupled to said video port FIFO and said display memory, for controlling page mode access to said display memory in video port FIFO cycles, wherein said control means controls said video port FIFO to transfer video data during a first predetermined number of memory cycles from said video port FIFO to said display memory during a video port FIFO cycle, said control means monitors said memory cycles during said video port FIFO cycle to detect a non-aligned memory cycle and interrupts a video port FIFO cycle if a non-aligned memory cycle is detected, said control means further controls said CRT FIFO to transfer video data during a second predetermined number of memory cycles from said display memory bus to said CRT FIFO during a CRT FIFO cycle, said control means monitors said memory cycles during said CRT FIFO cycle to detect a non-aligned memory cycle and shortens a subsequent video port FIFO cycle if a non-aligned memory cycle is detected, and said control means shortens said subsequent video port FIFO cycle by reducing said first predetermined number of memory cycles in a subsequent video port FIFO cycle.

Claim 8

A multimedia computer system for selectively generating video and graphics data for displaying a video image on at least a portion of a display and reducing an effect of non-aligned page misses during page mode memory access, said multimedia computer system comprising: a video port for receiving video data; a video port FIFO coupled to said video port for receiving and storing said video data; a display memory coupled to said video port FIFO for receiving said video data from at least said video port FIFO and for storing said video data; and a CRT FIFO coupled to said display memory and a control means for retrieving and storing at least a portion of said video data from a display memory; an output display port, coupled to said CRT FIFO for receiving and outputting said at least a portion of said video data from said CRT FIFO; and said control means, coupled to said video port FIFO and said display memory, for controlling page mode access to said display memory in video port FIFO cycles, wherein said control means controls said video port FIFO to transfer video data during a first predetermined number of memory cycles from said video port FIFO to said display memory during a video port FIFO cycle, said control means monitors said memory cycles during said video port FIFO cycle to detect a non-aligned memory cycle and interrupts a video port FIFO cycle if a non-aligned memory cycle is detected, said control means further controls said CRT FIFO to transfer video data during a second predetermined number of memory cycles from said display memory bus to said CRT FIFO during a CRT FIFO cycle, said control means monitors said memory cycles during said CRT FIFO cycle to detect a non-aligned memory cycle and shortens a subsequent video port FIFO cycle if a non-aligned memory cycle is detected, and said control means shortens said subsequent video port FIFO cycle by reducing said first predetermined number of memory cycles in a subsequent video port FIFO cycle.

Claim 9

The multimedia computer system of claim 5, further comprising: a display means, coupled to said output display port, for displaying an image generated from at least a portion of said video data.

Claim 10

The multimedia computer system of claim 6, wherein said display means is a cathode ray tube monitor.

Claim 11

The multimedia computer system of claim 6, wherein said display means is a flat panel display.

Claim 12

The multimedia computer system of claim 6, wherein said display means is a television monitor.

Claim 13

The multimedia computer system of claim 5, further comprising: a CPU for receiving, processing, and outputting at least text and graphics data; and a text and graphics controller coupled to said CPU and said control means for receiving text and graphics data; wherein said control means transfers text and graphics data from said text and graphics controller to said display memory during a CPU cycle.

Claim 14

The multimedia computer system of claim 5, wherein said control means transfers data accumulated in said video port FIFO when said control means interrupts an video port FIFO cycle to said display memory during a retrace interval of said video data from said video port.

Claim 17

The method of claim 12, further comprising the steps of: receiving text and graphics data from an external CPU in a text and graphics controller, and transferring text and graphics data from the text and graphics controller to the display memory during a CPU cycle.

Claim 18

The method of claim 12, further comprising the step of: transferring data accumulated in the video port FIFO when due to an interrupt in a video port FIFO cycle to the display memory during a retrace interval of the video data from the video port.