§
PatentCue
Patent Intelligence
Join Waitlist Sign In
Patent US5621241A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5621241A Expired / Lapsed US ⏱️ 0.0 years remaining

Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films

Assignee: Texas Instruments Inc
•
Filing: 1995-06-07
•
Granted: 1997-04-15
•
Expires: 2015-06-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.

Inventors

  • 👤 Manoj K. Jain

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 04:39
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 148 words
A semiconductor device having both high and low aspect ratio conductors on a common conducting level, said device comprising: (a) a layer of patterned conductors formed on a substrate and comprising a plurality of high aspect ratio conductors and a plurality of low aspect ratio conductors, said layer having a first thickness; (b) an HDP oxide layer overlying said patterned conductors and said substrate, said HDP oxide layer having a second thickness measured over said low aspect ratio conductors and a third thickness measured over said high aspect ratio conductors, said second thickness having a ratio to said third thickness of at least 1.5:1; and (c) an oxide polish layer overlying said HDP oxide layer, said polish layer having a substantially planar top surface, said layer of patterned conductors, HDP oxide layer, and oxide polish layer having a combined thickness of at least 150% of said first thickness.
Claim 2
Dependent Claim 148 words
A semiconductor device having both high and low aspect ratio conductors on a common conducting level, said device comprising: (a) a layer of patterned conductors formed on a substrate and comprising a plurality of high aspect ratio conductors and a plurality of low aspect ratio conductors, said layer having a first thickness; (b) an HDP oxide layer overlying said patterned conductors and said substrate, said HDP oxide layer having a second thickness measured over said low aspect ratio conductors and a third thickness measured over said high aspect ratio conductors, said second thickness having a ratio to said third thickness of at least 1.5:1; and (c) an oxide polish layer overlying said HDP oxide layer, said polish layer having a substantially planar top surface, said layer of patterned conductors, HDP oxide layer, and oxide polish layer having a combined thickness of at least 150% of said first thickness.
Claim 3
Dependent Claim 30 words
The semiconductor device of claim 1, wherein HDP oxide thickness, as measured in one or more gaps between said patterned conductors, is between 50% and 125% of said first thickness.
Claim 4
Dependent Claim 26 words
The semiconductor device of claim 1, further comprising a conformal dielectric seed layer overlying said patterned conductors and said substrate, and underlying said HDP oxide layer.
Claim 5
Dependent Claim 21 words
The semiconductor device of claim 3, wherein said conformal dielectric seed layer has a thickness of 300 Å to 1000 Å.
Claim 6
Dependent Claim 30 words
The semiconductor device of claim 1, wherein said oxide polish layer is comprised of materials selected from the group consisting of: PETEOS, BPSG, BSG, PSG, silane oxide, and combinations thereof.

References Cited (Backward Citations)

US4966865A Cited
US5381046A Cited
US5471091A Cited
US5510652A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-04-14 2000-10-14 2001-04-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-04-14 2004-10-14 2005-04-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-04-14 2008-10-14 2009-04-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag