US5621902A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller
Assignee: Lenovo Singapore Pte Ltd
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Filing: 1994-11-30
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Granted: 1997-04-15
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Expires: 2014-11-30
Abstract
Abstract A computer system having a peripheral controller interconnect (PCI) bus and an industry standard architecture (ISA), with ISA compatible devices coupled to the ISA bus, is provided with a first bridge coupled between the PCI and ISA buses. The first bridge has a first direct memory access (DMA) control circuit for controlling DMA transfers with the ISA devices. In order to achieve expanded compatibility with other types of devices, the system is also provided with an expansion bus, such as a Microchannel bus, with Microchannel compatible devices coupled to the Microchannel bus. A second bridge is coupled between the PCI and the Microchannel buses. This second bridge has a second DMA control circuit that controls DMA transfers with the ISA devices and with the Microchannel devices. Software disables the first DMA control circuit such that only the second DMA control circuit controls DMA transfers within the computer system.
Inventors
- 👤 Moises Cases
- 👤 Richard G. Hofmann
- 👤 Lance M. Venarchick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
218 words
A computer system comprising: a first bus and a second bus; first devices coupled to the first bus; second devices coupled to the second bus; a first bridge coupled between the first and second buses, the first bridge having: a first direct memory access (DMA) control circuit for controlling DMA transfers with the devices coupled to the second bus, said first DMA control circuit being capable of being in an enabled state and a disabled state; wherein said enabled state is characterized in that said first DMA control circuit controls DMA transfers with the devices coupled to the second bus and wherein said disabled state is characterized in that said first DMA control circuit does not control DMA transfers with the devices coupled to the second bus; a third bus; third devices coupled to the third bus; and a second bridge coupled between the first and third buses, the second bridge having: an alternate DMA control circuit that controls DMA transfers with the devices coupled to the first, second and third buses; and logic that disables the first DMA control circuit only when said first DMA control circuit is present in said system such that only the alternate DMA control circuit controls DMA transfers with devices coupled to the first, second and third buses within the computer system.
Claim 2
Dependent Claim
218 words
A computer system comprising: a first bus and a second bus; first devices coupled to the first bus; second devices coupled to the second bus; a first bridge coupled between the first and second buses, the first bridge having: a first direct memory access (DMA) control circuit for controlling DMA transfers with the devices coupled to the second bus, said first DMA control circuit being capable of being in an enabled state and a disabled state; wherein said enabled state is characterized in that said first DMA control circuit controls DMA transfers with the devices coupled to the second bus and wherein said disabled state is characterized in that said first DMA control circuit does not control DMA transfers with the devices coupled to the second bus; a third bus; third devices coupled to the third bus; and a second bridge coupled between the first and third buses, the second bridge having: an alternate DMA control circuit that controls DMA transfers with the devices coupled to the first, second and third buses; and logic that disables the first DMA control circuit only when said first DMA control circuit is present in said system such that only the alternate DMA control circuit controls DMA transfers with devices coupled to the first, second and third buses within the computer system.
Claim 3
Dependent Claim
35 words
The computer system of claim 1, wherein the first bus is a peripheral controller interconnect (PCI) bus, the second bus is an industry standard architecture (ISA) bus, and the third bus is a Microchannel bus.
Claim 4
Dependent Claim
33 words
The computer system of claim 2, wherein the first DMA control circuit includes control signal drivers, and wherein the disabling of the first DMA control circuit includes tristating of the control signal drivers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-14 | 2000-10-14 | 2001-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-14 | 2004-10-14 | 2005-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-14 | 2008-10-14 | 2009-04-15 | $7700.00 | Window Closed / Lapsed |