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Apparatus and method for controlling data transmissions in a communication network

Assignee: LG Electronics Inc
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Filing: 1995-10-11
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Granted: 1997-05-27
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Expires: 2015-10-11
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Abstract

Abstract An apparatus for controlling data transmissions in a communication network which includes a plurality of nodes connected to a common bus, each of said nodes having a communication processor with a memory and a bus control device associated with the processor. The apparatus comprises malfunction a detect control device provided in one of the nodes for detecting a malfunction in the network and generating a malfunction signal to every node over the bus when the malfunction is detected and an alarm to an operator for repair of the network in case of a network malfunction, a malfunction detect device provided in each of the other nodes for receiving the malfunction signal and controlling the connection with a bus diagnosing device provided in every node and responsive to the malfunction detect device for diagnosing whether the detected malfunction has occurred in its node and forcing the processor to stop its operation for data transmissions; and the malfunction detect device also forcing the bus control device to disconnect with the bus, thereby removing the malfunction in the network.

Inventors

  • 👤 Chang-ho Kim
  • 👤 Eog-woo Choi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:37
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/403; H04L43/00; H04L69/00; H04L69/40

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 305 words
An apparatus for controlling data transmissions in a communication network which includes a plurality of nodes connected to a common bus, each of said nodes having a communication processor with a memory and bus control means associated with the processor for transmitting data from the processor to the network over the bus, said bus control means including a direct memory access controller (DMAC) for accessing parallel data in the memory, means for converting from parallel data to serial data or vice versa, a bus control module for generating a bus acknowledge signal and responding to a bus request signal from the processor and a bus asserting signal from said bus control means during data transmission, and a bus driver for connection with the bus for data transmissions, the apparatus comprising: malfunction detect/control means provided in one of said nodes for detecting a malfunction in the network and generating a malfunction signal to said nodes including itself over the bus when the malfunction is detected; malfunction detect means provided in each of the other nodes for receiving said malfunction signal from the malfunction detect/control means over the bus; diagnosing means provided in every node, responding to the malfunction detect means for diagnosing whether the detected malfunction is occurred in its node; and wherein in the malfunctioned node, said diagnosing means forces the processor to stop its operation for data transmissions and the malfunction detect means or the malfunction detect/control means also forces the bus control means to disconnect with the bus, thereby removing the malfunction in the network; wherein, when said malfunction detect/control means continuously detects a malfunction in the network without receiving of a bus asserting signal, said malfunction detect/control means decides that the malfunction is occurred in the network itself and then produces an alarm to an operator of the network for repair thereof.
Claim 2
Independent Claim 305 words
An apparatus for controlling data transmissions in a communication network which includes a plurality of nodes connected to a common bus, each of said nodes having a communication processor with a memory and bus control means associated with the processor for transmitting data from the processor to the network over the bus, said bus control means including a direct memory access controller (DMAC) for accessing parallel data in the memory, means for converting from parallel data to serial data or vice versa, a bus control module for generating a bus acknowledge signal and responding to a bus request signal from the processor and a bus asserting signal from said bus control means during data transmission, and a bus driver for connection with the bus for data transmissions, the apparatus comprising: malfunction detect/control means provided in one of said nodes for detecting a malfunction in the network and generating a malfunction signal to said nodes including itself over the bus when the malfunction is detected; malfunction detect means provided in each of the other nodes for receiving said malfunction signal from the malfunction detect/control means over the bus; diagnosing means provided in every node, responding to the malfunction detect means for diagnosing whether the detected malfunction is occurred in its node; and wherein in the malfunctioned node, said diagnosing means forces the processor to stop its operation for data transmissions and the malfunction detect means or the malfunction detect/control means also forces the bus control means to disconnect with the bus, thereby removing the malfunction in the network; wherein, when said malfunction detect/control means continuously detects a malfunction in the network without receiving of a bus asserting signal, said malfunction detect/control means decides that the malfunction is occurred in the network itself and then produces an alarm to an operator of the network for repair thereof.
Claim 3
Dependent Claim 68 words
The apparatus claimed in claim 1, wherein a linker is provided between the DMAC and serial/parallel data converting means for permitting data transmission from the DMAC to the serial/parallel data converting means when the bus acknowledge signal is received from the bus control module and for producing a data transmission finishing signal to the bus control module to disconnect with the bus when the data transmission is finished.
Claim 4
Independent Claim 210 words
A method for controlling data transmission in a communication network which includes a plurality of nodes connected to a common bus, each of said nodes having a communication processor with a memory, bus control means for providing a bus acknowledge signal to the communication processor and malfunction diagnosing means for diagnosing a malfunction, one of said nodes further having malfunction detect/control means for detecting a malfunction and generating a malfunction signal and each of the other nodes further having malfunction detect means for detecting malfunctions, the method comprising the steps of: detecting in the malfunction/control means a malfunction in the network and producing a malfunction signal to every node over the bus; detecting the malfunction signal in the malfunction detect means in every node; determining whether the malfunction is occurred, in the malfunction diagnosing means in each node responding to the bus control means; stopping the operation of the processor for data transmission responding to the malfunction diagnosing means and disconnecting the bus control means from the bus by the malfunction detect means in the node where the malfunction is occurred; indicating the network malfunction to an operator of the network by the malfunction detect/control means when the malfunction is continuously detected without a bus asserting signal from any node.
Claim 5
Independent Claim 210 words
A method for controlling data transmission in a communication network which includes a plurality of nodes connected to a common bus, each of said nodes having a communication processor with a memory, bus control means for providing a bus acknowledge signal to the communication processor and malfunction diagnosing means for diagnosing a malfunction, one of said nodes further having malfunction detect/control means for detecting a malfunction and generating a malfunction signal and each of the other nodes further having malfunction detect means for detecting malfunctions, the method comprising the steps of: detecting in the malfunction/control means a malfunction in the network and producing a malfunction signal to every node over the bus; detecting the malfunction signal in the malfunction detect means in every node; determining whether the malfunction is occurred, in the malfunction diagnosing means in each node responding to the bus control means; stopping the operation of the processor for data transmission responding to the malfunction diagnosing means and disconnecting the bus control means from the bus by the malfunction detect means in the node where the malfunction is occurred; indicating the network malfunction to an operator of the network by the malfunction detect/control means when the malfunction is continuously detected without a bus asserting signal from any node.

References Cited (Backward Citations)

US4354226A Cited
US4608559A Cited
US5249183A Cited
US5299193A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-05-26 2000-11-25 2001-05-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-05-26 2004-11-25 2005-05-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-05-26 2008-11-25 2009-05-27 $7700.00 Window Closed / Lapsed

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