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US5636251A Expired / Lapsed US ⏱️ 0.0 years remaining

Receiver for a trellis coded digital television signal

Assignee: Zenith Electronics LLC
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Filing: 1996-01-29
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Granted: 1997-06-03
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Expires: 2016-01-29
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Abstract

Abstract A data receiver comprises a demodulator for recovering a received data signal comprising a stream of interleaved regularly spaced one-dimensional symbols of a phase invariant symbol constellation, each of the received symbols representing 3 bits, Z 0 , Z 1 , Z 2 produced by convolutionally coding a first data bit X 1 to derive bits Z 0 , Z 1 and precoding a second data bit X 2 to derive bit Z 2 . The received symbols are applied to a first decoder for estimating data bit X 1 and a bit Y 2 , Y 2 being applied to a postcoder for conversion to an estimate of data bit X 2 . The first decoder may comprise a Viterbi decoder or a 4-level slicer. In a preferred embodiment of the invention the received signal includes a plurality of regularly spaced synchronization intervals, each comprising a number of received symbols, and the second decoder is prevented from changing state during the synchronization intervals.

Inventors

  • 👤 Richard W. Citta
  • 👤 David A. Willming

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 07:23
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0045; H04L1/0054; H04L27/00; H04L27/32; H04L27/34; H04L27/3405; H04L27/3416; H04N; H04N21/00; H04N21/40; H04N21/41; H04N21/426

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 162 words
A data receiver comprising: means for developing a received data signal comprising a plurality of regularly spaced one-dimensional symbols of a phase variant symbol constellation, each of said symbols representing 3-bits Z 0 , Z 1 , Z 2 produced by coding a first data bit X 1 using a multi-state convolution coder to derive bits Z 0 , Z 1 and a second data bit X 2 using a modulo - 2 precoder to derive bit Z 2 , wherein bits Z 0 , Z 1 identify respective subsets (a-d) of said symbols, each of said subsets (a-d) comprising two equally spaced symbol values, and bits Z 1 , Z 2 identify respective pairs of said symbols each comprising two adjacent symbol values; decoder means for estimating data bit X 1 and a bit Y 1 from the received data signal; and a postcoder for generating an estimation of data bit X 2 in response to estimated bit Y 2 .
Claim 2
Dependent Claim 162 words
A data receiver comprising: means for developing a received data signal comprising a plurality of regularly spaced one-dimensional symbols of a phase variant symbol constellation, each of said symbols representing 3-bits Z 0 , Z 1 , Z 2 produced by coding a first data bit X 1 using a multi-state convolution coder to derive bits Z 0 , Z 1 and a second data bit X 2 using a modulo - 2 precoder to derive bit Z 2 , wherein bits Z 0 , Z 1 identify respective subsets (a-d) of said symbols, each of said subsets (a-d) comprising two equally spaced symbol values, and bits Z 1 , Z 2 identify respective pairs of said symbols each comprising two adjacent symbol values; decoder means for estimating data bit X 1 and a bit Y 1 from the received data signal; and a postcoder for generating an estimation of data bit X 2 in response to estimated bit Y 2 .
Claim 3
Dependent Claim 71 words
The receiver of claim 1 wherein said decoder means comprises a Viterbi decoder for estimating data bit X 1 and bit Y 2 from said received data signal in response to a determination of the most likely sequence of transitions between the states of said convolution coder and wherein said postcoder comprises a modulo-2 postcoder for converting said estimated bit Y 2 into an estimation of data bit X 2 .
Claim 4
Dependent Claim 52 words
The receiver of claim 1 wherein said decoder means comprises a four-level slicer for estimating data bit X 2 and bit Y 2 from said received data signal and wherein said postcoder comprises a modulo-2 postcoder for converting said estimated bit Y 2 into an estimation of data bit X 2 .
Claim 5
Dependent Claim 33 words
The data receiver of claim 1 wherein said received data signal includes a plurality of regularly spaced synchronization intervals and including means for preventing said postcoder from changing state during said synchronization intervals.
Claim 6
Dependent Claim 181 words
A data receiver comprising: means for developing a received data signal comprising M groups of independently coded interleaved one dimensional symbols of a phase variant symbol constellation, each of said groups including a plurality of regularly spaced symbols each representing 3 bits Z 0 , Z 1 , Z 2 produced by coding a first data bit X 1 with a coder comprising a multi-state convolutional encoder to derive bits Z 0 , Z 1 and a second data bit X 2 with a coder comprising a modulo-2 precoder to derive bit Z 2 , wherein bits Z 0 , Z 1 identify respective subsets (a-d) of said symbols, each of said subsets (a-d) comprising two equally spaced symbol values, and bits Z 1 , Z 2 identify respective pairs of said symbols each comprising two adjacent symbol values; means for reducing channel interference characterizing said received data signal; and a decoder operable for estimating data bits X 1 , X 2 in response to each symbol of each of said groups of symbols of said received interference reduced data signal.
Claim 7
Dependent Claim 181 words
A data receiver comprising: means for developing a received data signal comprising M groups of independently coded interleaved one dimensional symbols of a phase variant symbol constellation, each of said groups including a plurality of regularly spaced symbols each representing 3 bits Z 0 , Z 1 , Z 2 produced by coding a first data bit X 1 with a coder comprising a multi-state convolutional encoder to derive bits Z 0 , Z 1 and a second data bit X 2 with a coder comprising a modulo-2 precoder to derive bit Z 2 , wherein bits Z 0 , Z 1 identify respective subsets (a-d) of said symbols, each of said subsets (a-d) comprising two equally spaced symbol values, and bits Z 1 , Z 2 identify respective pairs of said symbols each comprising two adjacent symbol values; means for reducing channel interference characterizing said received data signal; and a decoder operable for estimating data bits X 1 , X 2 in response to each symbol of each of said groups of symbols of said received interference reduced data signal.
Claim 8
Dependent Claim 58 words
The data receiver of claim 5 wherein said decoder comprises a first decoder for estimating data bit X 1 and a bit Y 2 in response to each symbol of each of said groups of symbols and a second decoder for converting each of said estimated bits Y 2 into an estimation of data bit X 2 .
Claim 9
Dependent Claim 22 words
The data receiver of claim 6 wherein said first decoder comprises a Viterbi decoder and said second decoder comprises a modulo-2 postcoder.
Claim 10
Dependent Claim 22 words
The data receiver of claim 6 wherein said first decoder comprises a four-level slicer and said second decoder comprises a modulo-2 postcoder.
Claim 11
Dependent Claim 34 words
The data receiver of claim 6 wherein said received data signal includes a plurality of regularly spaced synchronization intervals and including means for preventing said second decoder from changing state during said synchronization intervals.
Claim 12
Dependent Claim 225 words
A data receiver comprising: means for developing a received data signal including a plurality of regularly spaced synchronization intervals and comprising M groups of independently coded interleaved one dimensional symbols of a phase variant symbol constellation, each of said groups including a plurality of regularly spaced symbols each representing 3 bits Z 0 , Z 1 , Z 2 produced by coding a first data bit X 1 with a coder comprising a multi-state convolutional encoder to derive bits Z 0 , Z 1 and a second data bit X 2 with a coder comprising a modulo-2 precoder to derive bit Z 2 , wherein bits Z 0 , Z 2 identify respective subsets (a-d) of said symbols, each of said subsets (a-d) comprising two equally spaced symbol values, and bits Z 1 , Z 2 identify respective pairs of said symbols each comprising two adjacent symbol values; means coupled to said means for developing for reducing channel interference characterizing said received data signal; a first decoder for estimating data bit X 1 and a bit Y 2 in response to each symbol of each of said groups of symbols, a second decoder for converting each of said estimated bits Y 2 into an estimation of data bit X 2 ; and means for preventing said second decoder from changing state during said synchronization intervals.
Claim 13
Dependent Claim 225 words
A data receiver comprising: means for developing a received data signal including a plurality of regularly spaced synchronization intervals and comprising M groups of independently coded interleaved one dimensional symbols of a phase variant symbol constellation, each of said groups including a plurality of regularly spaced symbols each representing 3 bits Z 0 , Z 1 , Z 2 produced by coding a first data bit X 1 with a coder comprising a multi-state convolutional encoder to derive bits Z 0 , Z 1 and a second data bit X 2 with a coder comprising a modulo-2 precoder to derive bit Z 2 , wherein bits Z 0 , Z 2 identify respective subsets (a-d) of said symbols, each of said subsets (a-d) comprising two equally spaced symbol values, and bits Z 1 , Z 2 identify respective pairs of said symbols each comprising two adjacent symbol values; means coupled to said means for developing for reducing channel interference characterizing said received data signal; a first decoder for estimating data bit X 1 and a bit Y 2 in response to each symbol of each of said groups of symbols, a second decoder for converting each of said estimated bits Y 2 into an estimation of data bit X 2 ; and means for preventing said second decoder from changing state during said synchronization intervals.
Claim 14
Dependent Claim 22 words
The data receiver of claim 10 wherein said first decoder comprises a Viterbi decoder and said second decoder comprises a modulo-2 postcoder.
Claim 15
Dependent Claim 22 words
The data receiver of claim 10 wherein said first decoder comprises a four-level slicer and said second decoder comprises a modulo-2 postcoder.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-06-02 2000-12-02 2001-06-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-06-02 2004-12-02 2005-06-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-06-02 2008-12-02 2009-06-03 $7700.00 Window Closed / Lapsed

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