Method of making a capacitor in a semiconductor device

Claim 1

A method of manufacturing a capacitor, comprising: providing a silicon substrate having a field region and an active region therein, said field region and said active region being positioned relative to each other in said silicon substrate; forming a field oxide film in said field region of said silicon substrate; forming a gate oxide film in said active region of said silicon substrate; sequentially forming first, second and third conducting layers on at least said field oxide film and said gate oxide film; forming a dielectric film on said third conducting layer; sequentially forming a fourth conducting layer and a fifth conducting layer on said dielectric film; sequentially etching said fifth conducting layer, said fourth conducting layer, said dielectric film, and said third conducting layer using a first etching process to form a first top plate and a second top plate on said field oxide film in said field region of said silicon substrate, said first top plate and said second top plate being positioned relative to each other on said field oxide film in said field region and having said fifth and fourth conducting layers; sequentially etching said second and first conducting layers using a second etching process to form a first bottom plate underneath said first top plate and a first portion of said dielectric film on said field oxide film in said field region and a second bottom plate underneath said second top plate and a second portion of said dielectric film on said field oxide film in said field region, said first bottom plate and said second bottom plate having said first, second and third conducting layers, thereby said first top plate, said first portion of said dielectric film, and said first bottom plate forming a first imaginary capacitor, and said second top plate, said second portion of said dielectric film, and said second bottom plate forming a second imaginary capacitor; forming an interlayer insulation film on said silicon substrate over said first and second imaginary capacitors and a region between said first and second imaginary capacitors; forming contact holes to expose a portion of each of said first and second top and bottom plates of said first and second imaginary capacitors; and using a metal contact process to electrically interconnect said first top plate of said first imaginary capacitor to said second bottom plate of said second imaginary capacitor, and to electrically interconnect said first bottom plate of said first imaginary capacitor to said second top plate of said second imaginary capacitor, thereby forming a real capacitor.

Claim 2

A method of manufacturing a capacitor, comprising: providing a silicon substrate having a field region and an active region therein, said field region and said active region being positioned relative to each other in said silicon substrate; forming a field oxide film in said field region of said silicon substrate; forming a gate oxide film in said active region of said silicon substrate; sequentially forming first, second and third conducting layers on at least said field oxide film and said gate oxide film; forming a dielectric film on said third conducting layer; sequentially forming a fourth conducting layer and a fifth conducting layer on said dielectric film; sequentially etching said fifth conducting layer, said fourth conducting layer, said dielectric film, and said third conducting layer using a first etching process to form a first top plate and a second top plate on said field oxide film in said field region of said silicon substrate, said first top plate and said second top plate being positioned relative to each other on said field oxide film in said field region and having said fifth and fourth conducting layers; sequentially etching said second and first conducting layers using a second etching process to form a first bottom plate underneath said first top plate and a first portion of said dielectric film on said field oxide film in said field region and a second bottom plate underneath said second top plate and a second portion of said dielectric film on said field oxide film in said field region, said first bottom plate and said second bottom plate having said first, second and third conducting layers, thereby said first top plate, said first portion of said dielectric film, and said first bottom plate forming a first imaginary capacitor, and said second top plate, said second portion of said dielectric film, and said second bottom plate forming a second imaginary capacitor; forming an interlayer insulation film on said silicon substrate over said first and second imaginary capacitors and a region between said first and second imaginary capacitors; forming contact holes to expose a portion of each of said first and second top and bottom plates of said first and second imaginary capacitors; and using a metal contact process to electrically interconnect said first top plate of said first imaginary capacitor to said second bottom plate of said second imaginary capacitor, and to electrically interconnect said first bottom plate of said first imaginary capacitor to said second top plate of said second imaginary capacitor, thereby forming a real capacitor.

Claim 8

A method of manufacturing a capacitor, comprising the steps of: providing a silicon substrate having a field region and an active region therein, said field region and said active region being positioned relative to each other in said silicon substrate; forming a field oxide film in said field region of said silicon substrate; forming a gate oxide film in said active region of said silicon substrate; sequentially forming first, second and third conducting layers on said silicon substrate, said conducting layers covering said field oxide film and said gate oxide film; forming a dielectric film on said third conducting layer; sequentially forming a fourth conducting layer and fifth conducting layer on said dielectric film; sequentially etching a first portion of said fifth, fourth conducting layers, said dielectric film and third conducting layer by a first etching process to form top plates having said fifth and fourth conducting layers on said field oxide film in said field region; sequentially etching a second portion of said second and first conducting layers by a second etching process to form a gate electrode on said gate oxide film in said active region, and to form bottom plates having said first, second and third conducting layers on said field oxide film in said field region, thereby forming first and second imaginary capacitors on said field oxide film having said top and bottom plates on said field oxide film, respectively, and said first and said second imaginary capacitors being located on said field oxide film in said field region and adjacent to each other therein; forming a diffusion region at said gate electrode by source and drain impurity ion implantation process; forming an interlayer insulation film on the entire structure including said first and second imaginary capacitors; forming contact holes to exposure said diffusion regions of said gate electrode in said active region and a portion of each of said top and bottom plates of said first and second imaginary capacitors in said field region; and performing a metal contact process to electrically interconnect said top plate of said first imaginary capacitor and said bottom plate of said second imaginary capacitor, and to electrically interconnect said bottom plate of said first imaginary capacitor and said top plate of said second imaginary capacitor, respectively, thereby forming a real capacitor.

Claim 9

A method of manufacturing a capacitor, comprising the steps of: providing a silicon substrate having a field region and an active region therein, said field region and said active region being positioned relative to each other in said silicon substrate; forming a field oxide film in said field region of said silicon substrate; forming a gate oxide film in said active region of said silicon substrate; sequentially forming first, second and third conducting layers on said silicon substrate, said conducting layers covering said field oxide film and said gate oxide film; forming a dielectric film on said third conducting layer; sequentially forming a fourth conducting layer and fifth conducting layer on said dielectric film; sequentially etching a first portion of said fifth, fourth conducting layers, said dielectric film and third conducting layer by a first etching process to form top plates having said fifth and fourth conducting layers on said field oxide film in said field region; sequentially etching a second portion of said second and first conducting layers by a second etching process to form a gate electrode on said gate oxide film in said active region, and to form bottom plates having said first, second and third conducting layers on said field oxide film in said field region, thereby forming first and second imaginary capacitors on said field oxide film having said top and bottom plates on said field oxide film, respectively, and said first and said second imaginary capacitors being located on said field oxide film in said field region and adjacent to each other therein; forming a diffusion region at said gate electrode by source and drain impurity ion implantation process; forming an interlayer insulation film on the entire structure including said first and second imaginary capacitors; forming contact holes to exposure said diffusion regions of said gate electrode in said active region and a portion of each of said top and bottom plates of said first and second imaginary capacitors in said field region; and performing a metal contact process to electrically interconnect said top plate of said first imaginary capacitor and said bottom plate of said second imaginary capacitor, and to electrically interconnect said bottom plate of said first imaginary capacitor and said top plate of said second imaginary capacitor, respectively, thereby forming a real capacitor.