Method of making split gate flash EEPROM cell

Claim 1

A method of making a flash EEPROM cell, comprising the steps of: removing a portion of a first oxide film and a nitride film which are sequentially formed on a silicon substrate through the etching process using a photoresist pattern as an etching mask to expose a portion of said silicon substrate; removing said photoresist pattern and then forming a second oxide film, by oxidizing the surface of said silicon substrate a portion of which is exposed; forming a recess on the surface of said silicon substrate from which said second oxide film is removed, by removing the exposed portion of said second oxide film using said nitride film a portion of which is removed as an etching mask, thereby the portion of said second oxide film covered with the nitride film a portion of which is removed remains intact; forming a drain region on said recess portion of said silicon substrate; forming a tunnel oxide film on said silicon substrate of said recess portion and then forming a first polysilicon layer on the entire structure; sequentially removing said first polysilicon layer, said nitride film a portion of which is removed, said tunnel oxide film and said first oxide film a portion of which is removed through the etching process using the mask for a floating gate electrode to form a floating gate made of said first polysilicon layer; implanting an impurity ion for controlling a threshold voltage to form a select gate channel region on said silicon substrate which is exposed on one side of said floating gate; forming a select gate oxide film and an interpoly oxide film and then forming a second polysilicon layer on the entire structure; and forming a control gate of split structure by patterning said second polysilicon layer through the etching process using the mask for a control gate electrode and then forming a source region on said silicon substrate which is exposed on one side of said control gate.

Claim 2

A method of making a flash EEPROM cell, comprising the steps of: removing a portion of a first oxide film and a nitride film which are sequentially formed on a silicon substrate through the etching process using a photoresist pattern as an etching mask to expose a portion of said silicon substrate; removing said photoresist pattern and then forming a second oxide film, by oxidizing the surface of said silicon substrate a portion of which is exposed; forming a recess on the surface of said silicon substrate from which said second oxide film is removed, by removing the exposed portion of said second oxide film using said nitride film a portion of which is removed as an etching mask, thereby the portion of said second oxide film covered with the nitride film a portion of which is removed remains intact; forming a drain region on said recess portion of said silicon substrate; forming a tunnel oxide film on said silicon substrate of said recess portion and then forming a first polysilicon layer on the entire structure; sequentially removing said first polysilicon layer, said nitride film a portion of which is removed, said tunnel oxide film and said first oxide film a portion of which is removed through the etching process using the mask for a floating gate electrode to form a floating gate made of said first polysilicon layer; implanting an impurity ion for controlling a threshold voltage to form a select gate channel region on said silicon substrate which is exposed on one side of said floating gate; forming a select gate oxide film and an interpoly oxide film and then forming a second polysilicon layer on the entire structure; and forming a control gate of split structure by patterning said second polysilicon layer through the etching process using the mask for a control gate electrode and then forming a source region on said silicon substrate which is exposed on one side of said control gate.