Maximized substrate design for grid array based assemblies

Claim 1

A method of packaging a Grid Array based integrated circuit device comprising the steps of: (a) forming stress relief slots in a substrate assembly to define adjacent individual units wherein said slots are formed around a substantial portion of the periphery of said unit such that portions remain to form support sites to attach the units to the substrate, wherein some of said slots define boundaries between adjacent ones of said units and wherein side edges of the slots that define boundaries between adjacent units are edges of such units, the slots serving to relieve stress due to thermal expansion during high temperature processing, said substrate having top and bottom surfaces wherein said top surface includes a plurality of conductive traces thereon; (b) affixing an integrated circuit device to the top surface of said substrate; (d) attaching a multiplicity of solder units to the bottom surface of the substrate in a predetermined grid pattern; (c) electrically coupling the device to said conductive traces, each said conductive trace being electrically connected to an associated solder unit on the bottom surface of said substrate; (e) encapsulating the die, electrical coupling, and conductive traces such that the cap and the substrate cooperate to seal the device from the outside environment; and (f) trimming said support sites such that the units are detached from the substrate as individual packages, wherein the trimming is accomplished by cutting between the stress relief slots such that a substantial portion of the periphery of each unit is formed by the stress relief slots.

Claim 2

A method of packaging a Grid Array based integrated circuit device comprising the steps of: (a) forming stress relief slots in a substrate assembly to define adjacent individual units wherein said slots are formed around a substantial portion of the periphery of said unit such that portions remain to form support sites to attach the units to the substrate, wherein some of said slots define boundaries between adjacent ones of said units and wherein side edges of the slots that define boundaries between adjacent units are edges of such units, the slots serving to relieve stress due to thermal expansion during high temperature processing, said substrate having top and bottom surfaces wherein said top surface includes a plurality of conductive traces thereon; (b) affixing an integrated circuit device to the top surface of said substrate; (d) attaching a multiplicity of solder units to the bottom surface of the substrate in a predetermined grid pattern; (c) electrically coupling the device to said conductive traces, each said conductive trace being electrically connected to an associated solder unit on the bottom surface of said substrate; (e) encapsulating the die, electrical coupling, and conductive traces such that the cap and the substrate cooperate to seal the device from the outside environment; and (f) trimming said support sites such that the units are detached from the substrate as individual packages, wherein the trimming is accomplished by cutting between the stress relief slots such that a substantial portion of the periphery of each unit is formed by the stress relief slots.

Claim 13

A method of maximizing substrate area on a strip for use in Grid Array based integrated circuit packages, comprising the steps of: designating substrate area into juxtaposed individual units wherein each individual unit corresponds to a substrate area for use in a single Grid Array based package; forming slots in said substrate along periphery of individual units wherein said slots are formed around a substantial portion of the periphery such that support sites remain to attach the units to the substrate; and whereby at least some of said slots serve to form boundaries between adjacent units after the units are detached from the substrate and to relieve stress during to thermal expansion in high temperature processing thereby eliminating excess substrate material between units and simplifying the unit separation operation, wherein said support sites are punched to separate the unit from the strip.

Claim 14

A method of maximizing substrate area on a strip for use in Grid Array based integrated circuit packages, comprising the steps of: designating substrate area into juxtaposed individual units wherein each individual unit corresponds to a substrate area for use in a single Grid Array based package; forming slots in said substrate along periphery of individual units wherein said slots are formed around a substantial portion of the periphery such that support sites remain to attach the units to the substrate; and whereby at least some of said slots serve to form boundaries between adjacent units after the units are detached from the substrate and to relieve stress during to thermal expansion in high temperature processing thereby eliminating excess substrate material between units and simplifying the unit separation operation, wherein said support sites are punched to separate the unit from the strip.