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Patent US5654913A successfully refreshed from Google Patents.
US5654913A
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Apparatus and method for extending data retention time of semiconductor storage circuit
Assignee: Panasonic Holdings Corp
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Filing: 1996-02-06
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Granted: 1997-08-05
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Expires: 2016-02-06
Abstract
Abstract In halt period during standby time, a cell plate node potential switching circuit changes the potential of a cell plate node to a low potential that is lower than a high potential adopted in a burst refresh operation. As a result, a potential difference between both ends of a PN junction of a memory cell transistor is decreased, thereby suppressing a leakage current flowing through the PN junction. Simultaneously, a word driver circuit changes the potential of a word line to a negative potential that is lower than a normal potential adopted in the burst refresh operation. As a result, an off state of the memory cell transistor is enhanced owing to decrease of a gate-source voltage thereof, thereby suppressing a leakage current flowing from the bit line to a charge storage node. Accordingly, a leakage current flowing through the PN junction of the memory cell transistor and a leakage current flowing from the bit line through the memory cell transistor to the charge storage node are both suppressed during the standby time. Thus, a refresh interval is elongated so as to decrease power consumption.
Inventors
- 👤 Tetsuyuki Fukushima
- 👤 Hiroyuki Yamauchi
- 👤 Toru Iwata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/408; G11C11/4085; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
322 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each memory cell including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the second electrode of the capacitor being connected to a cell plate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between the first electrode of the capacitor and the electrode of the memory cell transistor serving as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, a PN junction being formed between the charge storage node and the substrate, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time and storage of the charge is halted in a second period during the standby time, and the apparatus is further provided with: a cell plate potential switching circuit having an output terminal connected to the cell plate for setting a potential of the cell plate, in the first period, at a predetermined potential, and in the second period, at a potential which makes smaller a potential difference between both ends of the PN junction than that in the first period, and an electrode potential switching circuit connected to the control electrode of the memory cell transistor for setting a potential of the control electrode, in the first period, at a set potential, and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress a leakage current flowing through the PN junction and an off current flowing through the memory cell transistor during the standby time.
Claim 2
Independent Claim
322 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each memory cell including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the second electrode of the capacitor being connected to a cell plate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between the first electrode of the capacitor and the electrode of the memory cell transistor serving as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, a PN junction being formed between the charge storage node and the substrate, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time and storage of the charge is halted in a second period during the standby time, and the apparatus is further provided with: a cell plate potential switching circuit having an output terminal connected to the cell plate for setting a potential of the cell plate, in the first period, at a predetermined potential, and in the second period, at a potential which makes smaller a potential difference between both ends of the PN junction than that in the first period, and an electrode potential switching circuit connected to the control electrode of the memory cell transistor for setting a potential of the control electrode, in the first period, at a set potential, and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress a leakage current flowing through the PN junction and an off current flowing through the memory cell transistor during the standby time.
Claim 3
Dependent Claim
116 words
The apparatus of claim 1, wherein the memory cell transistor includes an NMOS transistor, the control electrode of the memory cell transistor is connected to a word line, and the electrode potential switching circuit includes: a word driver circuit for changing a potential of the word line between a potential for operation and that for standby, and a word line potential switching circuit for further setting the potential of the word line that has changed by the word driver circuit, in the first period, at the set potential, and in the second period, at a low potential that is lower than the set potential, so as to enhance the off state of the memory cell transistor.
Claim 4
Dependent Claim
81 words
The apparatus of claim 2, wherein the word line potential switching circuit includes first and second transistors connected in parallel to each other, and the first transistor is supplied with a ground potential and turned on in the first period so as to supply the ground potential to the word driver circuit, and the second transistor is supplied with the low potential and turned on in the second period so as to supply the low potential to the word driver circuit.
Claim 5
Dependent Claim
41 words
The apparatus of claim 1, further comprising: a timer circuit for distinguishing the first period and the second period during the standby time, and outputting a period signal to the cell plate potential switching circuit and the electrode potential switching circuit.
Claim 6
Dependent Claim
68 words
The apparatus of claim 1, wherein a potential of the substrate is set at a negative potential, and the cell plate potential switching circuit changes, in the second period, the potential of the cell plate to a low potential that is lower than the predetermined potential, so as to make smaller the potential difference between the both ends of the PN junction than that in the first period.
Claim 7
Dependent Claim
105 words
The apparatus of claim 5, further comprising: a first cell plate potential generating circuit connected to the cell plate potential switching circuit for generating the predetermined potential, a second cell plate potential generating circuit for generating the low potential and supplying the low potential to the cell plate potential switching circuit, and a diode disposed between the first cell plate potential generating circuit and the cell plate potential switching circuit and including an NMOS or a PMOS transistor for supplying the cell plate potential switching circuit with a potential obtained by slightly decreasing the predetermined potential generated by the first cell plate potential generating circuit.
Claim 8
Dependent Claim
105 words
The apparatus of claim 5, further comprising: a first cell plate potential generating circuit for generating the predetermined potential and supplying the predetermined potential to the cell plate potential switching circuit, a second cell plate potential generating circuit connected to the cell plate potential switching circuit for generating the low potential, and a diode disposed between the second cell plate potential generating circuit and the cell plate potential switching circuit and including an NMOS or a PMOS transistor for supplying the cell plate potential switching circuit with a potential obtained by slightly increasing the low potential generated by the second cell plate potential generating circuit.
Claim 9
Dependent Claim
26 words
The apparatus of claim 1, wherein the bit line is precharged to a supply potential or a half of the supply potential in the second period.
Claim 10
Dependent Claim
95 words
The apparatus of claim 1, wherein the memory cell transistor includes an NMOS transistor, the control electrode of the memory cell transistor is connected to a word line, the electrode potential switching circuit includes a word driver circuit for changing a potential of the word line between a potential for operation and that for standby, and the word driver circuit sets, always during the standby time, the potential of the word line at a low potential which is lower than the predetermined potential, so as to enhance the off state of the memory cell transistor.
Claim 11
Dependent Claim
149 words
The apparatus of claim 9, wherein the word driver circuit includes: a word drive line and a wire supplied with the low potential, a drive control transistor for connecting the word drive line to the word line, a negative potential control transistor for connecting the wire to the word line, a first transistor for turning on the drive control transistor and turning off the negative potential control transistor when a predetermined node has a predetermined high potential, and second and third transistors for connecting the predetermined node to the negative control transistor in the second period, and each threshold voltage of the negative potential control transistor and the second transistor is set at a predetermined voltage which is larger than a potential difference between the ground potential and the negative potential, and driving ability of the second transistor is set to be smaller than that of the third transistor.
Claim 12
Dependent Claim
180 words
The apparatus of claim 1, wherein the plural memory cells are divided into at least a first group and a second group, and the apparatus is further provided with: a timing control circuit for causing transition of the second group from the second period to the first period after transition of the first group from the first period to the second period, and charge redistribution means for, during the time till the transition of the second group from the second period to the first period after the transition of the first group from the first period to the second period, connecting the second electrode of the capacitor of the memory cell belonging to the first group to the second electrode of the capacitor of the memory cell belonging to the second group, so as to reuse charge between the second electrodes, and for connecting the control electrode of the memory cell transistor belonging to the first group to the control electrode of the memory cell transistor belonging to the second group, so as to reuse charge between the control electrodes.
Claim 13
Independent Claim
314 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each of the memory cells including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between the first electrode of the capacitor and the electrode of the memory cell transistor serving as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, a PN junction being formed between the charge storage node and the substrate, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time and storage of the charge is halted in a second period during the standby time, and the apparatus is further provided with: a substrate potential switching circuit having an output terminal connected to the substrate of the memory cell transistor for setting a potential of the substrate, in the first period, at a predetermined potential and in the second period, at a potential which makes smaller a potential difference between both ends of the PN junction than that in the first period, and an electrode potential switching circuit connected to the control electrode of the memory cell transistor for setting a potential of the control electrode, in the first period, at a set potential and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress a leakage current flowing through the PN junction and an off current flowing through the memory cell transistor during the standby time.
Claim 14
Independent Claim
314 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each of the memory cells including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between the first electrode of the capacitor and the electrode of the memory cell transistor serving as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, a PN junction being formed between the charge storage node and the substrate, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time and storage of the charge is halted in a second period during the standby time, and the apparatus is further provided with: a substrate potential switching circuit having an output terminal connected to the substrate of the memory cell transistor for setting a potential of the substrate, in the first period, at a predetermined potential and in the second period, at a potential which makes smaller a potential difference between both ends of the PN junction than that in the first period, and an electrode potential switching circuit connected to the control electrode of the memory cell transistor for setting a potential of the control electrode, in the first period, at a set potential and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress a leakage current flowing through the PN junction and an off current flowing through the memory cell transistor during the standby time.
Claim 15
Dependent Claim
124 words
The apparatus of claim 12, wherein the substrate potential switching circuit sets the potential of the substrate at a predetermined negative potential in the first period, and changes the potential of the substrate to a high potential that is higher than the negative potential in the second period, so as to make smaller the potential difference between the both ends of the PN junction than that in the first period, and the electrode potential switching circuit sets the potential of the control electrode of the memory cell transistor at the set potential in the first period, and in the second period, at a low potential that is lower than the set potential, so as to enhance the off state of the memory cell transistor.
Claim 16
Independent Claim
183 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, a potential of a substrate of the memory cell transistor is increased so as to make small a potential difference between both ends of a PN junction formed between the charge storage node and the substrate of the memory cell transistor, and the potential of the gate of the memory cell transistor is changed from the high potential to a predetermined low potential, thereby enhancing an off state of the memory cell transistor.
Claim 17
Independent Claim
183 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, a potential of a substrate of the memory cell transistor is increased so as to make small a potential difference between both ends of a PN junction formed between the charge storage node and the substrate of the memory cell transistor, and the potential of the gate of the memory cell transistor is changed from the high potential to a predetermined low potential, thereby enhancing an off state of the memory cell transistor.
Claim 18
Independent Claim
248 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each of the memory cells including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the second electrode of the capacitor being connected to a cell plate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between which serves as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time and storage of the charge is halted in a second period during the standby time, so as to extend the data retention time of the charge storage node of the semiconductor storage circuit, and the apparatus is further provided with a cell plate potential switching circuit having an output terminal connected to the cell plate for setting a potential of the cell plate, in the first period, at a predetermined potential and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress an off current flowing through the memory cell transistor during the standby time.
Claim 19
Independent Claim
248 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each of the memory cells including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the second electrode of the capacitor being connected to a cell plate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between which serves as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time and storage of the charge is halted in a second period during the standby time, so as to extend the data retention time of the charge storage node of the semiconductor storage circuit, and the apparatus is further provided with a cell plate potential switching circuit having an output terminal connected to the cell plate for setting a potential of the cell plate, in the first period, at a predetermined potential and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress an off current flowing through the memory cell transistor during the standby time.
Claim 20
Dependent Claim
55 words
The apparatus of claim 15, wherein the cell plate potential switching circuit sets the potential of the cell plate, in the first period, at the predetermined potential and in the second period, at a high potential that is higher than the predetermined potential, so as to enhance the off state of the memory cell transistor.
Claim 21
Dependent Claim
37 words
The apparatus of claim 15, wherein the memory cell transistor is formed out of a transistor having an SOI (silicon on insulator) structure including an insulator interposed between the control and other two electrodes and the substrate.
Claim 22
Independent Claim
135 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time, so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, a potential of a cell plate connected to the capacitor is changed to be high, thereby enhancing an off state of the memory cell transistor.
Claim 23
Independent Claim
135 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time, so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, a potential of a cell plate connected to the capacitor is changed to be high, thereby enhancing an off state of the memory cell transistor.
Claim 24
Independent Claim
231 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each of the memory cells including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between the first electrode of the capacitor and the electrode of the memory cell transistor serving as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time, and storage of the charge is halted in a second period during the standby time, and the apparatus is further provided with an electrode potential switching circuit connected to the control electrode of the memory cell transistor for setting a potential of the control electrode, in the first period, at a set potential, and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress an off current flowing through the memory cell transistor during the standby time.
Claim 25
Independent Claim
231 words
An apparatus for extending data retention time of a semiconductor storage circuit comprising a plurality of memory cells, each of the memory cells including a capacitor having a first electrode and a second electrode with an insulator sandwiched therebetween and a memory cell transistor having a control electrode and other two electrodes disposed on a substrate, the first electrode of the capacitor being connected to one of the two electrodes of the memory cell transistor, a node between the first electrode of the capacitor and the electrode of the memory cell transistor serving as a charge storage node, the other of the two electrodes of the memory cell transistor being connected to a bit line, wherein a predetermined amount of charge is stored in the charge storage node of at least one of the memory cells in a first period during standby time, and storage of the charge is halted in a second period during the standby time, and the apparatus is further provided with an electrode potential switching circuit connected to the control electrode of the memory cell transistor for setting a potential of the control electrode, in the first period, at a set potential, and in the second period, at a potential which enhances an off state of the memory cell transistor, so as to suppress an off current flowing through the memory cell transistor during the standby time.
Claim 26
Dependent Claim
59 words
The apparatus of claim 19, wherein the electrode potential switching circuit sets the potential of the control electrode of the memory cell transistor, in the first period, at the set potential, and in the second period, at a low potential that is lower than the set potential, so as to enhance the off state of the memory cell transistor.
Claim 27
Dependent Claim
37 words
The apparatus of claim 19, wherein the memory cell transistor is formed out of a transistor having an SOI (silicon on insulator) structure including an insulator sandwiched between the control and other two electrodes and the substrate.
Claim 28
Independent Claim
186 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, a potential of a cell plate connected to the capacitor is decreased, so as to make small a potential difference between both ends of a PN junction formed between the charge storage node and a substrate of the memory cell transistor, and then the potential of the gate of the memory cell transistor is switched from the high potential to a predetermined low potential, so as to enhance an off state of the memory cell transistor.
Claim 29
Independent Claim
186 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, a potential of a cell plate connected to the capacitor is decreased, so as to make small a potential difference between both ends of a PN junction formed between the charge storage node and a substrate of the memory cell transistor, and then the potential of the gate of the memory cell transistor is switched from the high potential to a predetermined low potential, so as to enhance an off state of the memory cell transistor.
Claim 30
Independent Claim
141 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time, so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, the potential of the gate of the memory cell transistor is changed from the high potential to a predetermined low potential, thereby enhancing an off state of the memory cell transistor.
Claim 31
Independent Claim
141 words
A method of extending data retention time of a semiconductor storage circuit, wherein a potential of a gate of an NMOS memory cell transistor is set at a high potential in a first period during standby time, so as to turn on the memory cell transistor, thereby transferring charge stored in a charge storage node disposed between the memory cell transistor and a capacitor to a bit line, and charge of the bit line is amplified by a sense amplifier, so that the amplified charge of the bit line be re-charged in the charge storage node via the memory cell transistor, and in a second period during the standby time, the potential of the gate of the memory cell transistor is changed from the high potential to a predetermined low potential, thereby enhancing an off state of the memory cell transistor.
Claim 32
Dependent Claim
52 words
The apparatus of claim 1, 22, 12, 14, 15, 18, 19, 23 or 11, wherein the first period during the standby time is a period when an intensive refresh operation is conducted, and the second period during the standby time is a halt period when the intensive refresh operation is not conducted.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |